Nec Corporation

Other

Renesas Electronics Corporation

Masamoto Tago

Tomohiro Nishiyama

Kaoru Mikagi

Tetuya Tao

Hirofumi Nakamura

Yoshihiro Nakagawa

Kei Tanaka

Yoshihiro Tomita

Koichiro Noguchi

Yoshio Kameda

Akihiro Dohya

Yoichiro Kurita

Kenji Takahashi

Norio Masuda

Toshihide Kuriyama

Takashi Ueda

Naoya Tamaki

Yoshimasa Kato

A hollow sealing structure includes a substrate, an element part provided on a first surface of the substrate, a cap that covers the element part, and a resin layer that covers the cap. The substrate includes a positioning part positioning the cap. The cap includes a fixation part being arranged at the positioning part and fixing the cap on the substrate. The resin layer is connected to the positioning part and the fixation part.

Hollow sealing structure

First semiconductor elementbeing buried in first insulating material; second semiconductor elementbeing covered by second insulating material; connection electrodebeing buried in first insulating materialarranged between circuit surface of first semiconductor elementand circuit surface of second semiconductor element; external connection terminalbeing arranged on lower surface of first insulating materialfacing in the same direction as lower surface of first semiconductor elementopposite to circuit surface thereof; connection electrodeforming a part of path for electrically connecting circuit surface of first semiconductor elementand circuit surface of second semiconductor elementto each other; first semiconductor elementand external connection terminalbeing electrically connected to each other by way of wireand viapassing through region of insulating layer other than region thereof burying connection electrode

Semiconductor device and method of manufacturing the same

[Problem to be Solved] A semiconductor element having fine pitch electrodes is mounted on a substrate at low cost without reducing the number of input-output terminals. [Solution] Electrodesfor electrical connection and first inductors, arranged between the electrodesin a manner neighboring the electrodes, for electromagnetic coupling are arranged on one main surface of the semiconductor element. On a substrate, second inductorsfor electromagnetically coupling with the first inductorsare arranged in positions corresponding to the first inductors. The semiconductor elementis mounted on the substrateso that the first and second inductorsandface each other. Only desired input/output signals among input/output signals of the semiconductor elementare inputted or outputted from the external electrodesof the substratein a manner being transmitted contactlessly by electromagnetic coupling between the first and second inductorsandwithout going through the electrodes

Semiconductor device, mounted substrate to be used in semiconductor device, and manufacturing method of mounted substrate

A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure the corresponding semiconductor wafers and that possess a mechanism for positioning the corresponding semiconductor wafers; and a probe card, arranged outside or in between the plurality of laminated semiconductor wafers so as to face the semiconductor wafers, that transmits a signal or power to the plurality of semiconductor wafers.

Semiconductor inspection apparatus, semiconductor wafer positioning method, and semiconductor wafer inspection method

A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

Semiconductor inspecting device and semiconductor inspecting method

There is provided a semiconductor device and a manufacturing method therefor, the semiconductor device requiring flip-chip mounting of a fine pitch electrode, wherein the fine electrode is easily manufactured, resin sealing is not required, and reliability can be improved. In the semiconductor device, one or more LSI chips (), having an insulating layer () surface and an electrode () surface on one side, and a substrate (), having an insulating layer () surface and an electrode () surface on one side, are bonded by having surfaces of the electrodes and surfaces of the insulating layers face each other via a bonding layer () made in a thin film form, in a region excluding the surfaces of the electrodes () and the surfaces of the insulating layers () in areas surrounding the electrodes.

Semiconductor device and method of manufacturing same

A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Semiconductor device, manufacturing method and apparatus for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer () is provided on one surface of a silicon base (). An electrode as the uppermost layer of the wiring layer () is provided with an external bonding bump (). A through-electrode () is formed in the base () for electrically connecting the wiring layer () and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip () by an internal bonding bump (). The thermal expansion coefficient of the silicon base () is equivalent to that of the semiconductor chip () and not more than that of the wiring layer ().

Semiconductor device, wiring substrate, and method for manufacturing wiring substrate

A wiring board (A) includes a first wiring portion (A) having a plurality of wiring layers () and external connecting bumps (), and at least one second wiring portion (A) having a plurality of contact plugs (). The second wiring portion is integrated with the first wiring portion such that each terminal () of the second wiring portion is in direct contact with one of the wiring layers of the first wiring portion. Hence, there is no risk to produce an internal stress caused by the diffused component of the solder bump in the junction portion between the second and first wiring portions. Accordingly, even when a semiconductor chip () of a low-k material is highly integrated on the wiring board, a highly reliable semiconductor device () can be obtained.

Semiconductor device and wiring board

A wiring board () includes a first wiring portion () having a plurality of wiring layers () and a plurality of external connecting bumps (), and a second wiring portion () integrated with the first wiring portion in the direction of thickness. The thermal expansion coefficient of the second wiring portion is made smaller than that of the first wiring portion, and equal to that of a semiconductor chip () to be mounted on the wiring board. This suppresses the internal stress resulting from the thermal expansion coefficient difference between the semiconductor chip and wiring board, and increases the reliability of a semiconductor device () obtained by mounting the semiconductor chip on the wiring board. The sizes of the opposing surfaces of the first and second wiring portions are also made equal. This requires only one second wiring portion to be formed even when improving the performance of the semiconductor device by mounting a plurality of semiconductor chips on the wiring board, thereby improving the performance at a low cost.

Semiconductor device, wiring board, and manufacturing method thereof

A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.

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Tokyo, Japan

Masamoto Tago