Nec Corporation

Masamichi Takagi

Hiroaki Inoue

Masayuki Mizuno

Sunao Torii

Masato Edahiro

Masaki Uekubo

Provided is a time series data device with which, when a process is changed, results of both a new and an old process are not outputted to the outside being mixed, and the results of the old process before and after the process is changed can be outputted to the outside. The device is equipped with: a first processing unit that executes a first process and outputs first results data; a second processing unit that executes a second process and outputs second results data; and a control unit that, when an instruction to change a process is received, determines whether the first process can be stopped, and generates first and second results data sets by appending identification information corresponding to process contents to the respective first and second results data.

Time series data device, time series data processing method and time series data processing program storage medium

Provided is a time series data processing device with which it is possible to change to a new process during the execution of an old process, and to control the selection and the output sequence of output data when processes are switched. A first processing unit executes a first process and generates first results data, and a second processing unit executes a second process and generates second results data. When an instruction to change processes is received from the outside, the first process in the first processing unit is stopped, and output of the first results data is prohibited. Then, the process in the first processing unit is changed from the first process to a third process and is started, and output of third results data is enabled. On the basis of third identification information appended to the third results data and second identification information appended to the second results data, the set of the third results data or the set of the second results data is selected, and the results data contained in the selected set of results data is output.

Time series data processing device, time series data processing method and time series data processing program storage medium

A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

Router, information processing device having said router, and packet routing method

A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Semiconductor integrated circuit and filter control method

Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.

Allocating task groups to processor cores based on number of task allocated per core, tolerable execution time, distance between cores, core coordinates, performance and disposition pattern

A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Semiconductor integrated circuit and filter and informational delivery method using same

An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

Apparatus and method for performing a screening test of semiconductor integrated circuits

A semiconductor integrated circuit comprises a plurality of cores () connected with an inter-connection network () and a test controller () which is connected with the inter-connection network () and which issues a test control request associated with the test of the core () via the inter-connection network (). The inter-connection network () is constituted of a plurality of adapters () which serve as connection interfaces of the plurality of cores () and the test controller (), respectively, and a plurality of routers () which connect the plurality of adapters (). The adapters () connected with the core () comprise a core testing unit for vicariously testing core () connected to itself based on the test control request received from the test controller () via the inter-connection network ().

Semiconductor integrated circuit and testing method therefor

A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.

Semiconductor integrated circuits and method of detecting faults of processors

An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

Growing community of inventors

Tokyo, Japan

Masamichi Takagi