Wuhan Tianma Micro-Electronics Co., Ltd

Nec Corporation

Nec Electronics Corporation

Nlt Technologies, Ltd.

Tianma Japan, Ltd.

Nec Lcd Technologies, Ltd.

Xiamen Tianma Display Technology Co., Ltd.

Nec Corporation and Nec Electronics Corporation

Masamichi Shimoda

Jiro Yanase

Yojiro Matsueda

Katsumi Abe

Yoshihiro Nonaka

Genshiro Kawachi

Tomohiko Otose

Hiroshi Tanabe

Shinya Niioka

Katsuyuki Fujikura

Masayuki Jumonji

Soichi Saito

Koichi Iguchi

Shift registers output high-level pulses each having a length of two or more horizontal periods one after another with a transfer step of one horizontal period. The shift register is controlled by a first clock signal and a second clock signal in m phases of clock signals. The shift register includes a high-level output thin-film transistor, a low-level output thin-film transistor and a buffer thin-film transistor. The buffer thin-film transistor receives a control signal having a pulse width and a cycle same as the first clock signal in a period where an output terminal is outputting a low-level potential. High-duties of the first clock signal and the second clock signal are expressed as PW/mH, where PW represents pulse widths of the first clock signal and the second clock signal and H represents one horizontal period. On-duties of all the thin-film transistors are not more than PW/mH.

Scanning circuit

A display device determines a gray level for a first pixel based on video data, determines whether the first pixel is in a first deterioration mode or a second deterioration mode following the first deterioration mode based on a driving history of the first pixel, determines a data signal to be supplied to the first pixel based on the gray level and the driving history of the first pixel with reference to first adjustment information for the first deterioration mode in a case of determining that the first pixel is in the first deterioration mode, and determines a data signal to be supplied to the first pixel based on the gray level and the driving history of the first pixel with reference to second adjustment information for the second deterioration mode in a case of determining that the first pixel is in the second deterioration mode.

Display device and method of controlling the same

A display device includes a deterioration evaluation region including dummy pixels and a display region. A control circuit determines a gray level for a first display pixel and determines whether the first display pixel is in a first deterioration mode or a second deterioration mode based on a driving history of the first display pixel. The control circuit determines, in the first deterioration mode, a data signal to be supplied to the first display pixel based on the gray level and the driving history of the first display pixel. The control circuit determines, in the second deterioration mode, a data signal to be supplied to the first display pixel based on the gray level, the driving history of the first display pixel, and measurement results about a current-voltage characteristic acquired from dummy pixels in the deterioration evaluation region of the same color as the first display pixel.

A display device includes a display pixel circuit including a display light-emitting element, a reference light-emitting element, and a display driving circuit. The display pixel circuit is configured to control light emission of the display light-emitting element based on a data signal in accordance with video data. The reference light-emitting element is precluded from the control in accordance with video data. The display driving circuit is configured to acquire a reference signal indicating a current-voltage characteristic of the reference light-emitting element, acquire a characteristic signal indicating the current-voltage characteristic of the display light-emitting element, and generate a signal indicating a degree of deterioration of the display light-emitting element based on a difference of the characteristic signal from the reference signal.

Display device

A display device includes a display region including display pixels, dummy pixels disposed outside the display region, light blocking films covering the dummy pixels. The display region includes a first region and a second region having a lower display pixel density than the first region. A control circuit is configured to supply the display pixels in the second region with driving current higher than driving current for the first region for the same grayscale level specified in image data, supply each of the dummy pixels with the same data signal as a data signal for the associated display pixel in the second region, measure deterioration of the light-emitting element of each of the dummy pixels, and adjust data signals for the display pixels in the second region associated with the dummy pixels based on results of the measurement.

Display device and terminal device

A display device includes a pixel circuit on a substrate, a data line to transmit a data signal for the pixel circuit on the substrate, a power supply line, and an extra voltage supply line different from the power supply line and the data line. The pixel circuit includes a driving transistor to control an amount of electric current supplied to a light-emitting element, a storage capacitor between a gate terminal of the driving transistor and the power supply line, a first switching transistor between the light-emitting element and the driving transistor, a second switching transistor between a source terminal of the driving transistor and the data line, and a third switching transistor between the source terminal of the driving transistor and the extra voltage supply line. The third switching transistor supplies a signal voltage different from the data signal to the driving transistor from the extra voltage supply line.

A display device includes a pixel circuit on a substrate, a data line configured to transmit a data signal for the pixel circuit on the substrate, and a monitoring circuit. The pixel circuit includes a driving transistor configured to control an amount of electric current supplied to a light-emitting element, and a first switching transistor disposed between the light-emitting element and the driving transistor. The first switching transistor switches between supplying and not supplying the light-emitting element with electric current from the driving transistor. The monitoring circuit monitors a signal at a monitoring point located between the driving transistor and the first switching transistor in the pixel circuit.

A driver is configured to maintain a threshold compensation transistor to be ON to write a threshold compensation voltage to a storage capacitor in a threshold compensation period, and write a data signal to the storage capacitor in a data write period after the threshold compensation period. A pulse width of control signal is twice or more as long as the data write period. The driver circuit is configured to turn ON a first transistor with a start edge of a first control signal pulse before the data write period starts, maintain the first transistor to be ON and turn ON a second transistor with a start edge of a second control signal pulse to start the data write period, and turn OFF the first transistor with an end edge of the first control signal pulse to end the data write period.

A display device includes a display region including display pixels, a control circuit, a first power line pattern, and a second power line pattern. The display region includes a first region and a second region having a lower display pixel density than the first region. The control circuit is configured to supply pixel circuits in the first region with a first power supply potential through the first power line pattern, supply pixel circuits in the second region with a second power supply potential higher than the first power supply potential through the second power line pattern, and supply light-emitting elements of the display pixels in the second region with driving current higher than driving current for the display pixels in the first region for a same grayscale level specified in image data.

A circuit includes a flip-flop included in a multi-stage shift register and a control element. The flip-flop includes an output field-effect transistor, a first field-effect transistor configured to operate to supply one of a high potential and a low potential to the gate of the output field-effect transistor, and a second field-effect transistor configured to operate to supply the other one of the high potential and the low potential to the gate of the output field-effect transistor. The control element is configured to operate to make an electric current flow between the gate and a power supply in the opposite direction of an off-leakage current from at least either one of the first field-effect transistor and the second field-effect transistor in a period where the first field-effect transistor and the second field-effect transistor are off.

Circuit including flip-flop and control element

A display device includes a pixel circuit on a substrate, a data line on the substrate, the data line being configured to transmit a data signal for the pixel circuit, a monitoring line on the substrate, the monitoring line being different from the data line, and a monitoring circuit. The monitoring circuit is configured to monitor a signal at a monitoring point on a path of the data signal with the monitoring line, and supply a correction signal in place of the data signal to the pixel circuit via the monitoring line and the monitoring point in response to detection of transmission failure of the data signal.

A liquid crystal display device of IPS mode includes an array of pixels arranged in a matrix pattern by crossing a plurality of video signal lines and a plurality of scanning signal lines each other. Each of the pixels is provided with at least a switching element. A transparent insulating film is provided on both signal lines, and a plurality of pixel electrodes, common electrodes and common lines are provided on the transparent insulating film. The common lines are formed in a grid-shaped pattern such that a first group of the common lines is made of a first conductor having lower reflectivity against optical light than that of metal while a second group of the common lines is made of a second conductor including a metal layer such that said first group and said second group are crossing each other along said video signal lines and said scanning signal lines.

Liquid crystal display device and electronic apparatus using the same

A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

Bidirectional shift register and display device using the same

Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

Semiconductor circuit and display apparatus employing the same

There is disclosed a shift register comprising a bootstrap circuit that outputs a voltage of the supply voltage to the output when the voltage of a first node becomes higher or lower than the supply voltage. The shift register comprises: two or more transistors connected in series to the first node; a device for supplying the voltage to a second node between the transistors such that the voltage between the drains and sources of the transistors becomes below the supply voltage; a first input transistor connected to the first node, and the gate electrode thereof is connected to a first input terminal as well; and an output transistor connected to the output terminal and the clock signal while having the gate electrode connected to the first node, wherein the gate electrode of the output transistor is not opened except for the bootstrap period.

Growing community of inventors

Kanagawa, Japan

Masamichi Shimoda