Fujitsu General Limited

Masamichi Nakajima

Masayuki Kobayashi

Hayato Denda

Junichi Onodera

Asao Kosakai

Seiji Matsunaga

Toru Aida

Takushi Kimura

Hideyuki Ohmori

Eizo Nishimura

Nobuyuki Takagi

The image quality correcting circuit according to the present invention is made up of a mean value computerfor computing the mean value of the luminance levels of every plural picture element of a video signal inputted to a video signal input terminal, an occurrence frequency counterfor counting the occurrence frequency data of plural luminance levels computed by the mean value computer, a linear interpolatorfor forming a correcting characteristic line based on the output points of the counted value from the occurrence frequency counter, and an image quality corrector, and wherein the linear interpolatorprovides the correcting characteristic line consisting of a linearly interpolated series of continuous segments, which are obtained by sequentially connecting the luminance levels of an x-axis and the occurrence frequencies on a y-axis, and the image quality correctorcorrects the video signals inputted from the video signal input terminalaccording to the linearly interpolated correcting characteristic line.

Image quality correcting circuit

When a voltage oscillator oscillates abnormally and a PLL circuit stops operating, in order to return to normal operation quickly, presence/absence of a comparison signal (fc) outputted from a frequency divider ( ) is detected, and at times when there is no comparison signal (fc), an output signal of a phase comparator ( ) is forcibly controlled to a low level temporarily, and an oscillation frequency of a voltage control oscillator ( ) is decreased. The present invention is suitable for generation of a sampling clock of a wide range which is used when digitally processing analog image signals, and for the like

PLL circuit which compensates for stoppage of PLL operations

An image processor containing an EPROM ( ) stored with coefficient data for image enlargement and reduction, coefficient read controllers ( ) for reading out coefficient data from the EPROM ( ) according to an enlargement/reduction selection signal, a variable horizontal characteristic filter ( ) for executing either image enlargement or image reduction according to the coefficient data, a variable vertical characteristic filter ( ) also for executing either image enlargement or image reduction according to the coefficient data, a frame memory ( ), a contour correcting circuit ( ), and selectors ( ). When image enlargement is selected by selectors ( ), input video signals are processed by the contour correcting circuit ( ), the frame memory ( ), and the filters ( ) in this order while, when image reduction is selected, input video signals are processed by the same in the reverse order. The portion which should not undergo contour enhancement does not undergo contour enhancement during image enlargement, and high frequency components enhanced by contour correction during image reduction do not disappear and adequate contour correction, even when either processing image enlargement or reduction, is selected.

Image processor

A dual-loop PLL circuit is provided with a clamping circuit an A/D conversion circuit a reference color burst outputting circuit a PLL circuit and phase detecting circuit The phase of a reference color burst KK outputted from the circuit is changed at a slice level SL, and the level SL is changed by a reference phase value in the phase detecting circuit The sampling clocks outputted from the PLL circuit to the A/D conversion circuit are converted to a signal of a frequency of 4 Fsc, and the phase of the signal can be changed continuously by using the reference phase value. In addition, since the phase of the sampling clocks can be adjusted to a desired value and the output signal of the A/D conversion circuit can be converted onto a prescribed color difference signal by a signal conversion circuit and outputted, the color difference signals can be demodulated easily with high accuracy.

Dual-loop PLL circuit and chrominance demodulation circuit

In a moving image correcting circuit for a display unit wherein a motion vector detecting portion detects inter-frame motion vectors and a moving image correcting position corrects the display positions of subfields for pixels in blocks, based on the detection values, the picture quality is protected from being degraded by preventing the output of an erroneous motion vector due to noise in, or fluctuation of, the input image signal or else preventing the erroneous motion vector, even if output from the motion vector detecting portion, from entering the moving image correcting portion.

Moving image correcting circuit for display device

A motion vector difference detection stage detects a difference D in motion vector between a current frame and a succeeding frame and a difference D in motion vector between a preceding frame and current frame. A latched circuit outputs the motion vector S of the inputted current frame as a motion vector S in the case where both of the absolute values of the differences D and D does not exceed a preset value L , and outputs the motion vector S of the frame preceding the corresponding frame as a motion vector S in the case where at least one of the absolute values of the differences D and D exceeds the preset value L . The latched circuit outputs a motion vector of 0 as a motion vector S in the case where both of the absolute values of the differences D and D exceed the preset value L and also the absolute value of the sum of the differences D and D exceeds the preset value L . When a change in motion vector is small, the motion vector of the corresponding frame carries out dynamic image correction. When a change in motion vector is large, the small motion vector of the preceding frame or the motion vector of 0 carries out dynamic image correction.

Motion vector processing circuit

In a subfield drive method, two subframes of the least brightness are arranged adjacently to each other to select and light up the display device in terms of the change in image brightness in the time axial direction. When, for example, the level of original signal changes from 7 to 8 or from 8 to 7, SF , SF , SF and SF are selected as subframes for level 8, and SF , F and SF are selected as subframes for level 7. This prohibiting any continuous lighting or non-lighting at the levels 7 and 8, there is no substantial change in brightness nor degradation of picture quality at that time. Any distortion of moving image (pseudo contour) is removed by the correction circuit having the frame memory that delays by one frame, the correction constant set circuit that outputs correction data, and the adder that adds the correction data to the original image signal.

Drive method and drive circuit of display device

A display device which displays a multilevel gradation image by dividing a frame into a plurality of subfields in respect of time and by allowing the subfields corresponding to the luminance levels of the input image signals to emit light, comprising a motion vector detection unit which detects the motion vector which expresses the motion of a block from one frame to the next, a high speed dynamic image correction unit and a law speed dynamic image correction unit which correct the input image signal by dynamic image correcting means which are suitable for the respective cases when the value of the detected motion vector is larger than a preset value S and when it is smaller than the preset value S and output the corrected input image signal, and a switching unit which elects either the output signal of the high speed dynamic image correction unit or the output signal of the law speed dynamic image correction unit to output the selected signal to the display in accordance with whether or not the value of the detected motion vector is larger than the preset value S. As a result, both the high speed dynamic image part and the low speed dynamic image part of the image can be optimally corrected.

Dynamic image correction method and dynamic image correction circuit for display device

The present invention is concerned with a PLL comprising the phase comparator,, loop filter,, VCO,and loop counter,, wherein there are further provided a prediction window circuit,for outputting HWIN (prediction window signal) for predicting the point at which the REF (reference signal) is generated, an omission compensation circuit,for detecting the omission of the REF at the time when HWIN is outputted and outputting d.VARX (the second correction signal) to offset the phase difference between d.REFX (the first correction signal) and the VAR (comparison signal) so that the phase comparator,outputs the signals Ph,and Ph,corresponding to the phase difference between the VAR and the d.REFX and the signals Ph,and Ph,corresponding to the phase difference between d.REFC and d.VARX when the omission of the REF has occurred, thereby enabling proper compensation for omission to be made and stable CLK (clock) to be generated even when VCO,having a very wide frequency variation range is used. Further, a circuit for generating the gate control signal Gc by advancing the phase of the VAR by 1 clock so that not only the 3-state signal corresponding to the phase difference between the REF and VAR can be outputted but also the 3-state buffers, which can be controlled in active state according to the signal Gc can be made available, whereby accurate control voltage corresponding to the phase difference can be outputted to the VCO to generate stable CLK even when the phase difference between the REF and VAR is close to 0.

Phase-locked loop

In an error diffusion processing unit to get a false half tone diffusing in the surroundings the luminance error between the original picture element signal quantizedly input and the preceding data, one dot of said signal is converted into plural picture elements. The respective picture elements (pixels) thus converted are compared with the prior data to detect the luminance error, which will then be weighted by multiplying it with certain coefficient to give, for instance, the reproduced error in one line past, that in one dot past and further the reproduced error a in one-line and one-dot past, which will respectively be added to the original pixels. Producing a false tone by error variance in unit of pixel enables to display the half tone without expanding the half tone display area beyond required dot number.

Drive for a display device

In a display device in which each group of plural drive elements takes charge of the drive of plural picture elements (pixels) and the display luminance changes as the number of sustaining pulses changes that are supplied to a plasma display panel, a constant emission luminance characteristic is maintained by increasing the number of sustaining pulses for a larger load when the display load factor is large, and decreasing the number of sustaining pulses for a smaller load when the display load factor is small. When displaying a multi-tone image by a subfield drive method, a display area detect circuit allows the display of an image with constant luminance characteristic despite the variation of the display load factor, and prevents the deterioration of tone characteristic due to the subfield drive method, and further, a half tone display circuit allows the decrease of the bit number thereby simplifying the configuration of the display area detect circuit.

Drive circuit for display device

Coupled to an error variance circuit 11 is an emission luminance characteristic acquisition circuit 20 that counts up, at a display number counter 21, the display number in the single or plural frames of the respective bits of image data by the counters, M in number, corresponding to said bits, then solves for display area percentage (Sk) dividing, at a display area percentage operation part 22, the display dot number as counted at a display number counter 21, by total dot number, and acquires the luminance deviation characteristic for each bit by means of an emission luminance deviation characteristic measuring part 24. The luminance deviation thus obtained is renewed for each frame and transferred to the error variance circuit 11, and processed for error variance on the basis of the emission luminance characteristic to be output at PDP. At low level, on the other hand, the luminance deviation is rendered either fixed type luminance deviation or emission luminance level more or less higher than the actual one to reduce the diffusion noise particularly at the low level image portion thereby obtaining a more natural image.

Error variance processing equipment for display device

An error variance circuit, wherein a reproduced error, as detected at an error detection circuit, is added to the image signal of the input signal picture element of n bits, and wherein a variance output signal is converted into a signal of m (.ltoreq.n-l) bits and outputted to a display panel, includes a clear circuit that clears error at each frame and forcibly reduces the prior error to zero thus preventing excessive noise from preceding frames and non-image duration causing flickering of picture.

Growing community of inventors

Kanagawa-ken, Japan

Masamichi Nakajima