Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Masamichi Ishihara

Hidetoshi Iwai

Kazuyuki Miyazawa

Yasushi Takahashi

Toshiyuki Sakuta

Gen Murakami

Tetsuro Matsumoto

Takashi Shinoda

Kazuya Ito

Ichiro Anjoh

Kousuke Okuyama

Hisashi Nakamura

Yasunori Yamaguchi

Masaya Muranaka

Hisao Katto

Tetsu Udagawa

Satoshi Oguchi

Hiromi Matsuura

Kazumichi Mitsusada

Shigetoshi Sakomura

Hiroyuki Uchiyama

Kunihiro Tsubosaki

Ryoichi Hori

Toshitsugu Takekuma

Yoshihisa Koyama

Kazumasa Yanagisawa

Kunihiko Nishi

Kazunari Suzuki

Masahiro Ichitani

Ryosuke Kimoto

Yasuhiro Kasama

Junichi Arita

Eiji Miyamoto

Akihiko Iwaya

Michio Tanimoto

Toshio Suzuki

Hidetomo Aoyagi

Haruo Ii

Takeshi Kizaki

Wataru Arakawa

Taisei Jin

Shunji Koike

Yoshinobu Nakagome

Hiroshi Satoh

Masanori Tazunoki

Youichi Matsuno

Atsusi Nozoe

Toshitugu Takekuma

Kiyoshi Inoue

Kazuhiko Kajigaya

Yutaka Ito

Katsutaka Kimura

Hirotaka Nishizawa

Toshio Sasaki

Kazuyoshi Oshima

Toshio Sugano

Toshio Yamada

Takashi Sato

Fumio Mizuno

Satoru Ito

Yukihide Suzuki

Masahiro Yamamura

Seiichiro Tsukui

Jiro Sawada

Kunihiko Ikuzaki

Tadao Kaji

Toshio Maeda

Takashi Araki

Tsuneo Ito

Osamu Sakai

Shinobu Takeura

Noboru Shiozawa

Norihiko Kasai

Yukio Yamamoto

Yoshiaki Ouchi

Ichirou Anjou

Hinoko Kurosawa

Yasuo Mori

Toshitugu Takemuma

Tomoshi Matsumoto, Deceased

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

Masami Nei

Akirahiko Yoshida

Kazuya Itoh

An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

Dynamic type semiconductor memory device

Semiconductor integrated circuit device, and process and apparatus for

A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Semiconductor device with lead structure on principal surface of chip

An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

Semiconductor memory having both a refresh operation cycle and a normal

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (103) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

Method of making mask pattern data and process for manufacturing the mask

Semiconductor memory having a refresh operation cycle and operating at a

Semiconductor device

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Sealed stacked arrangement of semiconductor devices

Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Method of fabrication of semiconductor integrated circuit device

Semiconductor device with lead structure within the planar area of the

Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Semiconductor integrated circuit device having output and internal

An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

Semiconductor integrated device and wiring correction arrangement

Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

Growing community of inventors

Hamura, Japan

Masamichi Ishihara