Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Renesas Technology Corp.

Masami Usami

Satoru Isomura

Masamori Kashiyama

Kazuhiro Akimoto

Masato Iwabuchi

Katsumi Ogiue

Kinya Mitsumoto

Hiroshi Murayama

Hitoshi Abe

Yoshikuni Kobayashi

Kazuo Tanaka

Mitsuaki Katagiri

Atsuo Watanabe

Takahide Ikeda

Akihisa Uchida

Nobuo Tamba

Toshiyuki Kikuchi

Toshiro Hiramoto

Shun Kawabe

Kenji Ujiie

Takeo Uchiyama

Toru Koizumi

Koichi Ishii

Takasi Oomori

Shigeharu Murata

Yoshino Sakai

A flip-chip BGA is disclosed which exhibits an excellent high-speed electric transmission characteristic while minimizing the formation of voids in sealing resin filled between a semiconductor chip and a wiring substrate. A silicon chip is flip-chip-mounted on a package substrate, and in a central area of a main surface of the silicon chip are arranged a power supply circuit, an input/output circuit, and plural bonding pads, while in the other area than the central area are arranged solder bumps in a matrix form, the solder bumps being electrically connected to the bonding pads through Cu wiring. Of the solder bumps, solder bumps for input/output power supply and solder bumps for the input and output of a data signal are arranged in a first area adjacent to the central area, and solder bumps for address signal input are arranged in a second area located outside the first area.

Semiconductor device

A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.

Semiconductor integrated circuit device including an improved separating

A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.

Hold-type latch circuit with increased margin in the feedback timing and

A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.

Semiconductor integrated circuit device and digital processor employing

Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Semiconductor integrated circuit device with two variable delay lines in

Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.

Vector processor performing data operations in one half of a total time

Semiconductor device for a ram disposed on chip so as to minimize

A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.

Semiconductor memory device having a timing generator circuit which

Growing community of inventors

Ohme, Japan

Masami Usami