Renesas Electronics Corporation

Renesas Technology Corp.

Other

Mitsubishi Denki Kabushiki Kaisha

Ryoden Semiconductor System Engineering Corporation

Masami Nakajima

Tetsushi Tanizaki

Hiroyuki Kondo

Kazushi Sugiura

Yukikazu Matsuo

Yoshihiro Okuno

A semiconductor device according to the present invention includes: a memory unit provided with a lower-order memory and a cache memory to cache a data stored in the lower-order memory; a power control circuit to control power supply of the lower-order memory; and a bus master to access the data stored in the memory unit after locking the bus. When the power supply of the lower-order memory is cut off at the time of occurrence of a mishit of the cache memory, the power control circuit restores the power supply of the lower-order memory, and the memory unit outputs a response to the access to the bus master. The bus master once releases the lock of the bus according to the response from the memory unit and reexecutes the access with the bus locked, after the restoration of the power supply of the lower-order memory is completed.

Semiconductor device and memory access control method

The disclosed invention enables the operation of an MIMD type, an SIMD type, or coexistence thereof in a multiprocessor system including a plurality of CPUs and reduces power consumption for instruction fetch by CPUs operating in the SIMD type. A plurality of CPUs and a plurality of memories corresponding thereto are provided. When the CPUs fetch instruction codes of different addresses from the corresponding memories, the CPUs operate independently (operation of the MIMD type). On the other hand, when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, that is, operate in the SIMD type, the instruction code read from one of the memories by one access is parallelly supplied to the CPUs.

Data processing device with multiple CPUs operating as an SIMD type

This invention provides a data processing device capable of operating a plurality of processing modules in parallel. Processes following a processing flow are assigned to the plural processing modules, respectively, and at least two of the processing modules are capable of running a same process. A network includes an arbitration circuit that, upon receiving a packet from a processing module, according to a process number attached to the packet, selects a processing module out of the processing modules capable of running the process, and outputs the packet to the selected processing module. This thus allows for autonomous transfer of a packet between each processing module and makes it possible to operate the processing modules in parallel.

Data processing device

When free bank information representing that a bank is not used by a PE and outputted from a PE controller coincides with used bank information representing that a bank is used for data transfer and outputted from a bus controller, a memory controller controls LM-bankstoand a switching network so as to enable all communications. Therefore, data reading and data writing by the PE is performed in parallel with the data transfer with the outside, so that processing time of the PE can be reduced.

Processor enabling input/output of data during execution of operation

A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in accordance with the decoding result of the instruction decoder. Therefore, the number of instructions that can be executed in parallel per cycle may be increased while at the same time the capacity of the instruction memory is reduced.

Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator

A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

Semiconductor memory device with built-in self test circuit operating at high rate

It assumes that 'SO' represents a state, in which that data in a responsible region storing the data to be accessed most frequently by the corresponding processor is updated in a cache memory to be controlled by a cache device, and other data is stored in other cache memory. In this case, one or more cache devices controlling each of the remaining cache memories changes the state of the data in a region other than the responsible region of the cache memory controlled by itself from 'SN' to &#x201c;I&#x201d; (invalid). Therefore, in the case where the data designated by the same address is shared by the plurality of cache memories, the data can be invalidated in the cache memories other than the cache memory corresponding to the processor including the designated address in its own responsible region. Therefore, a data sharing rate can be low.

Cache device controlling a state of a corresponding cache memory according to a predetermined protocol

A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flops and the input of another is one stage of a 2-input EXOR gate even in a critical path thereby shortening the critical path.

Synchronous counter

When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes. Therefore, because the for-synchronization-circuit enabling signal is not received from the outsides but is produced, a circuit area of a semiconductor integrated circuit can be efficiently used.

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Tokyo, Japan

Masami Nakajima