Kabushiki Kaisha Toshiba

Masami Murakata

Masaaki Yamada

Mutsunori Igarashi

Fumihiro Minami

Takashi Ishioka

Takashi Mitsuhashi

Hideki Takeuchi

Takahiro Aoki

Reiko Nojima

Toshihiro Akiyama

Hiroshi Tanaka

Naohito Kojima

The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent so as to make the numbers of '0' and '1' in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same

A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

Method for distributing clock signals to flip-flop circuits

A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program

Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method

With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same

An improved semiconductor integrated circuit and power supply wiring designing method and system is described in which the wiring resources have been effectively used without oppressing the same. The semiconductor integrated circuit in accordance with the present invention comprising: a semiconductor chip; an integrated circuit formed within the semiconductor chip; a first power supply pad; a first power supply wiring having a cyclic pattern formed on the integrated circuit for the purpose of supplying power to the integrated circuit from the first the power supply pad; a second power supply pad; and a second power supply wiring having an acyclic pattern formed on the integrated circuit for the purpose of supplying supplementary power to the integrated circuit from the second power supply pad. Particularly the second power supply wiring is connected to the second power supply pad in a binary tree fashion in order to maintain a voltage drop under a required level of each region of the integrated circuit as defined by the first power supply wiring.

Semiconductor integrated circuit and power supply routing method and

An automatic placement method for arranging logic cells on a chip, having a setting step for setting an evaluation function, target values thereof, placement improvement methods, and a range of a satisfaction level of each evaluation function, a calculating step for calculating a difference between a value of each evaluation function and, its target value, an improving step for selecting one of the placement improvement methods to optimize the evaluation function having the largest difference and then executing the placement improvement method; wherein the above processing is repeatedly executed over a required number of times, the range of each evaluation function is set by using probabilistic fluctuation each processing, and the range of each evaluation function is further narrowed with every processing.

Automatic placement method for arranging logic cells

In an automatic cell-layout arranging system for a polycell logic LSI, polycells are initially arranged in the form of cell arrays on a chip substrate. Connection paths for wiring lines among the polycells are then determined in accordance with cell-wiring requirements, so as to maximally satisfy a predetermined object function, thereby obtaining an LSI logic circuit capable of performing the desired function. A processor unit calculates a first number 'N' of wiring lines actually extending through each of the cell arrays, and a second number 'ml' representing an allowable number of through-lines for each cell array. Thereafter, this unit calculates a third number 'K' representing the difference 'ml-N' between the first and second numbers. When a certain cell array where the third number 'K' is less than zero is included in the cell arrays, the standard cells are rearranged on the chip substrate such that the third number 'K' is increased to zero or more than zero, thereby maximally eliminating the need to use through-cells for passing wiring lines through the cell arrays.

Growing community of inventors

Kanagawa-ken, Japan

Masami Murakata