Sony Corporation

Masami Goseki

Kazushi Sato

Naofumi Yanagihara

Kenji Komori

Satoshi Mitsuhashi

Tetsuo Kaneko

Takao Terao

Hiroshi Sugawara

Rajesh Kumar Dixit

Kazuhiro Takeda

Akihide Ogawa

A video signal processor for improving a detection precision of Y motion and C motion, preventing erroneous judgment, and preventing deterioration of image quality without being influenced by the band of the luminance signal or the phase of a sub-carrier of chroma. The processor includes a provisional 3D Y/C separation motion detection circuit, extracting Y signals of a current frame and a past frame based on composite video signals of three adjacent lines of the current frame and the past frame, detecting Y motion in accordance with a difference of Y signals of the current frame and the past frame by a Y motion detection unit, outputting a Y motion detection signal MVD, detecting C motion by a C motion detection unit based on Y signals of three adjacent lines in the current frame, outputting a C motion detection signal MVD, and selecting, according to the motion detection signals MVDand MVD, the difference of the C signals separated from the current frame and the past frame or a predetermined valueto generate a C motion coefficient.

Video signal processor and TV receiver using the same

An adaptive comb filter small in circuit scale and simple in circuit constitution is provided. The frequency band component of chrominance signal is extracted from a composite color video signal by a bandpass filter. The extracted chrominance signal is delay by a delay circuit by one horizontal period. A subtraction output is obtained by a first subtracting circuit between the output signal of the bandpass filter and the output signal of the delay circuit. An addition output is obtained by a adding circuit between the output signal of the bandpass filter and the output signal of the delay circuit. A correlation detecting circuit is provided that outputs a binary signal kbased on a relationship between the output of the first subtracting circuit and the output of the adding circuit. This binary signal kand a signal kobtained by delaying this binary signal kby a second delay circuit by one horizontal period are supplied to an arithmetic block. From an operational result between the signals kand k, the arithmetic block outputs a select signal for performing switching control on a selector switch circuit that switches between the output of the bandpass filter and the output of the first subtracting circuit and outputs the switched output. Then, the arithmetic block obtains the chrominance signal from the selector switch circuit.

Comb filter and a video apparatus

It is targeted to prevent picture quality deterioration in the output picture information proper to the interlaced scanned picture and that ascribable to interlaced scanning. To this end, a decimating inverse discrete cosine transform unitapplies inverse orthogonal transform to four low-range coefficients in the horizontal direction and eight coefficients in the vertical direction among the respective coefficients of an orthogonal transform block of the compressed picture information of the input high resolution picture.

Picture decoding method and apparatus using a 4&#xd7;8 IDCT

An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers , ten field, compression, inverse discrete-cosine transform multipliers , eight selectors , eight selectors , eight buffers , eight sign multipliers , a control section, eight adders , and eight buffers . The control section controls the selectors , selectors , buffers and sign multipliers in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors , selectors , buffers and sign multipliers is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders add the values output from the selectors , selectors , buffers and sign multipliers . The buffers store the values output from the adders

Inverse discrete-cosine transform apparatus

An MPEG downdecoder is to be provided which eliminates dephasing of pixels of moving picture data without losing properties inherent in a picture obtained on interlaced scanning. In the case of a field DCT mode, 4&times;4 decimating IDCT is executed for phase correction for a &frac14; pixel for pixels in the vertical direction of a top field and for phase correction for &frac34; pixel for pixels in the vertical direction of a bottom field. In the case of a frame DCT mode, the totality of coefficients of a DCT block are IDCTed and separated into two pixel blocks associated with interlaced scanning. The low-frequency components of these two pixel blocks are IDCTed to synthesize the two pixel blocks. The pixels in the vertical direction of the top field are phase-corrected by a &frac14; pixel, while those in the vertical direction of the bottom field are phase-corrected by a &frac34; pixel.

Picture decoding method and apparatus

An MPEG downdecoder is to be provided which eliminates pixel dephasing with the field DCT mode and the frame DCT mode without detracting from picture characteristics proper to interlaced pictures. To this end, a decimating IDCT unit effectuates 4&times;4 decimating IDCT if the DCT mode is the field mode. If the DCT mode is a frame mode, a decimating IDCT unit effectuates IDCT on the totality of coefficients of a DCT block to separate the coefficients into two pixel blocks associated with interlaced scanning. The decimating IDCT unit executes DCT on the separated two pixel blocks. The low-frequency components of the two pixel blocks are processed with IDCT and the two pixel blocks are synthesized.

An MPEG downdecoder is to be provided which eliminates dephasing of pixels during motion compensation to prevent deterioration of the picture quality ascribable to motion compensation. MPEG data of a high resolution picture are processed by decimating IDCT devices with 4&times;4 decimating IDCT to decode data of standard resolution picture data. In the case of the field motion prediction mode, a motion compensation device interpolates respective pixels of a macro-block of reference picture data stored in a frame memory to generate a macro-block constituted by pixels of &frac14; pixel precision. In the case of the frame motion prediction mode, a motion compensation device interpolates respective pixels of macro-block of reference picture data stored in the frame memory to generate a macro-block constituted by pixels of &frac14; pixel precision.

An MPEG downdecoder which eliminates picture quality deterioration ascribable to motion compensation. A decimating inverse discrete cosine transform unit performs 4&times;4 decimating IDCT if the DCT mode is the field mode. If the DCT mode is the frame mode, a decimating IDCT unit for frame mode applies IDCT to the totality of the coefficients of the DCT block and separates the DCT block into two pixel blocks in order to cope with the interlaced scanning. Each of the separated pixel blocks is processed with DCT. To reference picture data, pixels are interpolated using orthogonal transform by motion compensation units to generate virtual upper-order picture data of high resolution, which is processed with motion compensation. The motion-compensated virtual upper-order picture data is orthogonal transformed to decimate pixels to generate reference picture data used for addition.

In a ring oscillator type VCO in which plural stages of inverter circuits are cascade-connected to each other so as to constitute a positive feedback loop, delay amounts for both a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal. These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage of the inverter circuit is arranged by three-stage inverters made of load transistors and driver transistors, and the control voltage is applied to the load transistors of the two adjoining inverters among the three-stage inverters.

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Tokyo, Japan

Masami Goseki