Panasonic Intellectual Property Management Co., Ltd.

Masami Funabashi

Akinori Shinmyo

Syuji Kato

A switching circuit includes a first input terminal, an output terminal, and a first circuit that switches between outputting and not outputting, to the output terminal, a first voltage that is inputted to the first input terminal. The first circuit includes a first transistor and a second transistor that are connected in series between the first input terminal and the output terminal and a first voltage-dividing circuit that divides the first voltage and supplies the first voltage thus divided to a common node between the first transistor and the second transistor.

Switching circuit and imaging device

A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Noise cancelling circuit and data transmission circuit

A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n&#x2265;2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n&#x2212;1) stages to the respective gates of the (n&#x2212;1)-th through first stages of the cascode transistors in descending order of potential.

Growing community of inventors

Osaka, Japan

Masami Funabashi