Semiconductor Energy Laboratory Co., Ltd.

Toa Nenryo Kogyo Kabushiki Kaisha

Masami Endo

Yoshiyuki Kurokawa

Takayuki Ikeda

Daisuke Kawae

Hiroki Dembo

Takuro Ohmaru

Kakuro Kokubo

Takayuki Inoue

Hideo Hirabayashi

Kazuaki Ohshima

Daijiro Hosogai

Jun Koyama

Munehiro Kozuma

Yoshinobu Nakamura

Yutaka Shionoiri

Hidetomo Kobayashi

Seiichi Yoneda

Tatsuji Nishijima

Hidekazu Miyairi

Toshihiko Saito

Tadafumi Ozaki

A memory device which stores a large amount of data is provided. The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and first to third wirings. The first transistor includes an oxide semiconductor in a channel formation region, the second transistor includes silicon in a channel formation region, and the third transistor includes silicon in a channel formation region. The first capacitor is provided in the same layer as the first transistor. A region of the second capacitor and a region of the first capacitor overlap with each other. The thickness of a dielectric of the second capacitor is preferably larger than the thickness of a dielectric of the first capacitor.

Memory device

A semiconductor device capable of retaining data for a long time is provided. A semiconductor device includes a first transistor including a first insulator, a first oxide semiconductor, a first gate, and a second gate; a second transistor including a second oxide semiconductor, a third gate, and a fourth gate; and a node. The first gate and the second gate overlap with each other with the first oxide semiconductor therebetween. The third gate and the fourth gate overlap with each other with the second oxide semiconductor therebetween. The first oxide semiconductor and the second gate overlap with each other with the first insulator therebetween. One of a source and a drain of the first transistor, the first gate, and the fourth gate are electrically connected to the node. The first insulator is configured to charges.

Semiconductor device, storage device, resistor circuit, display device, and electronic device

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Storage element, storage device, and signal processing circuit

A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.

Memory element and signal processing circuit

A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

Semiconductor circuit, method for driving the same, storage device, register circuit, display device, and electronic device

To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

Memory circuit including oxide semiconductor devices

An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.

Inverter circuit, power converter circuit, and electric vehicle

A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.

Integrated circuit, method for driving the same, and semiconductor device

An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

Programmable logic device

It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

Transistor with an oxide semiconductor layer

An object is to detect reflected light from an object accurately and to improve accuracy of capturing an image in a photosensor included in a display panel. In the display panel including a photosensor, when an image of an object is captured, light is emitted from a light source to the object and reflected light enters the photosensor. In the case where the incident light is too strong with respect to sensitivity of the photosensor, luminance of the light source is lowered. In the case where the incident light is too weak with respect to sensitivity of the photosensor, the luminance of the light source is increased.

Growing community of inventors

Kanagawa, Japan

Masami Endo