Kabushiki Kaisha Toshiba

Bridgestone Corporation

Hitachi, Ltd.

Fujitsu Corporation

Kla Tencor Corporation

Masami Aoki

Tohru Ozaki

Toyoshi Kawada

Takeshi Hamamoto

Katsuhiko Hieda

Kazumasa Sunouchi

Hiroshi Takato

Takashi Yamada

Soichi Inoue

Akihiro Nitayama

Haruo Koizumi

Hisashi Mori

Mariko Habu

Hitomi Kawaguchiya

Mitsuhiro Noguchi

Yusuke Kohyama

Hisashi Kaneko

Akira Nishiyama

Kenji Yasuda

Hirofumi Inoue

Junichi Wada

Satoshi Inaba

Takamasa Usui

Masahiko Hasunuma

Martin Plihal

Takashi Ohashi

Max Gerald Levy

Atsushi Murakoshi

Allen Park

Toshiyuki Utsuki

Bruce Walter Porth

Yoshiaki Matsushita

Kazuya Matsuzawa

Ellis Chang

Osamu Arisumi

Hideki Kitano

Naoyuki Shigyo

Yutaka Ishibashi

Kazuhiko Nishiyama

Yasuhiko Sato

Sachiko Kobayashi

Kazuko Yamamoto

Makoto Yoshimi

Chikazu Yokoi

Michael John Van Riet

Takahiro Matsuse

Takashi Kitamura

Shigeru Kambayashi

Victor R Nastasi

Takamasa Ishikawa

Emily E Fisch

Kazuto Fujita

Sayuri Hashizume

Mamoru Terauchi

Norio Matsumoto

Kunio Morimoto

Morimitsu Iwai

Paul C Buschner

Kenichi Okazaki

Tomoyuki Shimaguchi

Chris Chih-Chien Young

Tahru Ozaki

Takefumi Yokokura

Akiko Nikki

Kazumi Sawano

A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a 'no match'. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.

Scanner performance comparison and matching using design and defect data

This invention relates to a tire-rim assembly which is easily produced at low cost, excellent in durability and capable of notably reducing road noise, and more particularly to a tire-rim assembly comprising a pneumatic tire (), a rim () and a sponge member () disposed in a tire internal cavity () defined by the pneumatic tire () and the rim (), characterized in that the sponge member () has a specific gravity of higher than 0.06 but not higher than 0.25 and/or an air permeability of not higher than 5 cc/cm/sec.

Tire-rim assembly and sponge member used in the same

An optical device includes an optical waveguide, an optical element, and a resin layer disposed between the optical waveguide and the optical element. The resin layer is formed of a photocurable material alone or in combination with a thermosetting material and includes an optical interconnect for optically connecting the optical waveguide and the optical element. The optical interconnect has a higher refractive index than a region of the resin layer around the optical interconnect. A method for producing the optical device includes providing the photocurable material between the optical waveguide and the optical element, partially irradiating the photocurable material with light to form the optical interconnect, and secondarily irradiating the overall photocurable material with light to cure the overall resin layer.

Optical device and method for producing the same

Magnetic disc storage unit for electronic computer

According to the present invention, drive voltage pulses are applied between a pair of electrodes by driving a first power source having a specific voltage from a state in which the electrodes are maintained at the potential of a reference power source that is different from the potential of the ground power source, and then returning it to the reference power source. As a result, the gas discharge current or capacitance charging and discharging current accompanying the application of the drive voltage pulses is prevented from flowing to the first power source line. The above-mentioned gas discharge current or capacitance charging and discharging current resulting from the application of the drive voltage pulses flows to the first power source or the reference power source electrically separated from the ground power source, and does not flow to the ground power source line, so no noise is generated on the first power source.

Plasma display panel device

A flat display device includes a display panel, a driver integrated circuit chip provided adjacent to the display panel in electrical connection thereto, and a heat sink provided adjacent to the display panel, wherein the heat sink carries thereon the driver integrated circuit chip.

Flat display device

A module, for mounting a driver IC constituting a drive circuit of a display apparatus using a flat display panel, is disclosed, which includes a driver IC chip for driving the display electrodes of the flat display panel and a wiring board electrically connected with the driver IC chip. A module for mounting the driver IC having this configuration comprises a first wiring unit formed with a drive power source system wiring for supplying a power source voltage, which is input to the driver IC chip, for driving the flat display panel through the driver IC chip; a second wiring unit formed with a control system wiring for supplying various signals, which are input to the driver IC chip, for controlling the driver IC chip; and a third wiring unit formed with an output terminal wiring taken out from the driver IC chip and connecting to the display electrodes of the flat display panel.

Module for mounting driver IC

A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver successively supplies scanning pulses to the scanning electrodes with scanning timing, and an address driver supplies address pulses according to display data to the address electrodes in synchronism with the scanning timing. The address electrodes include first and second address electrodes disposed adjacent to each other. The address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.

Display apparatus with flat display panel

A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

Semiconductor apparatus formed by SAC (self-aligned contact)

The present invention relates to a driver IC packaging module and a parallel plate type display device incorporating the same, and a chassis structure for an IC module having a high heat radiation effect or a flat display device having a high heat radiation efficiency can be achieved. There is provided a driver IC packaging module which comprises a driver IC chip for driving a display electrode of the flat display panel , a substrate on which the driver IC chip is mounted, a flexible substrate having output wirings on one end of which connection terminals are provided and on the other end of which output terminals are provided so as to connect electrically at least the display electrode and output pads of the driver IC chip , and a structure in which the output pads of the driver IC chip and the connection terminals of the flexible substrate are connected directly and also a direction of exposed surfaces of the output terminals of the flexible substrate connected to the display electrode and a direction of a driver IC chip mounting surface on the substrate are directed oppositely.

Driver IC packaging module and flat display device using the same

A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Self-aligned trench capacitor capping process for high density DRAM cells

A semiconductor memory device includes a semiconductor substrate having convex and concave portions locally formed in a surface thereof. An anti-reflection film serves as a first mask member and is formed on the semiconductor substrate. A photoresist is formed on the anti-reflection film. The anti-reflection film is partially removed using an opening formed by patterning the photoresist so as to expose an upper surface of the convex portion. The convex portion is etched using the photoresist and the anti-reflection film left in the concave portion. The anti-reflection film and the photoresist are removed, thereby obtaining the semiconductor substrate worked in a self-alignment manner.

Manufacturing method of a semiconductor memory device

In a stack type memory cell of 8F,, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Semiconductor device with high integration density and improved performance

A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.

Semiconductor memory device having bitlines of common height

An air filter suitably usable in an air cleaner, room air-conditioner or especially in car air-conditioners in which air is driven at a high speed. The air filter is made of a pleated polyurethane foam having on one or both sides thereof a three-dimensional network skeletal structure of micro cells.

Pleated air filter and method for producing same

Growing community of inventors

Tokyo, Japan

Masami Aoki