Freescale Semiconductor,inc.

Motorola Corporation

Masami Aiura

Satoshi Takahashi

Yuichi Nakatani

Kanji Egawa

Osamu Saionji

Shintaroh Murakami

Takashi Kumazaki

A charge control circuit for a battery charger that quickly detects an attachment state of a battery pack. The battery charger starts charging a battery pack and performs first and second temperature estimation processes. Then, the battery charger performs a first attachment detection process and when determining whether a battery is connected performs a third temperature estimation process. The battery charger performs a second attachment detection process and when determining whether the battery is connected performs a fourth temperature estimation process. The battery charger performs a third attachment detection process and when determining whether the battery is connected ends a single temperature scan and then repeats the routine starting from the first temperature estimation process.

Charge control circuit and battery charger including a charge control circuit

A PWM controller for adjusting an output voltage of a buck and boost converter includes a first saw wave generator, which generates a first saw wave in accordance with the level of the output voltage. A first comparator coupled to the first saw wave generator compares the first saw wave with a first reference voltage and generates a first pulse. A peak hold circuit coupled to the first saw wave generator holds a peak value of the first saw wave. A second saw wave generator coupled to the peak hold circuit generates a second saw wave having a lower limit value that is the peak value of the first saw wave. A second comparator coupled to the second saw wave generator compares the second saw wave with the first reference voltage and generates a second pulse.

Controller for buck and boost converter

A battery charging circuit and a battery charger that stabilizes operation when switching between charging modes. The battery charging circuit includes first and second transistors that form a current mirror circuit with an output transistor. The source terminal of the first transistor is connected to a first resistor, and the source terminal of the second transistor is connected to a second resistor. Each source terminal is connected to a switch circuit, which controls switching between a trickle charge mode and a fast charge mode. The supply of current to the first and second resistors from the discrete transistors reduces the difference in phase lag resulting from the CR time constant and stabilizes operation in the trickle charge and the fast charge modes.

Battery charging circuit and battery charger

A battery charging circuit that stabilizes operation when switching between charge modes includes first and second transistors. The first transistor has a source connected to a first switch circuit. The first switch circuit connects the second transistor to either one of first and second external terminals. A mode switch circuit generates a switch signal for switching from a trickle charge mode to a fast charge mode. The mode switching circuit provides the switching signal to a comparison circuit. After a predetermined time elapses, the mode switching circuit provides the switching signal to the switch circuit. The comparison circuit lowers a current restriction reference voltage, which determines a charging current value, and returns the current restriction reference voltage to its original value after switching modes.

Battery charging circuit

A steam iron includes a sensor for detecting and measuring movement of the steam iron. The sensor is coupled to an actuator that regulates the flow of steam via a valve located between a steam chamber and steam outlets. The sensor can detect movement in three directions (X, Y, Z) and adjust steam generation based on speed of movement of the iron and tilt angle. A pre-heater is used to pre-heat water in a water chamber. The pre-heated water is provided to a steam chamber where it is later converted to steam.

Steam iron with acceleration and tilt detection

A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

Method for detecting output short circuit in switching regulator

A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

Circuit and method for reducing output noise of regulator

A power supply circuit that accurately generates output voltages with the same regulator includes a regulator for generating a first output voltage from an input voltage. A first switch circuit, connected to the regulator, selectively outputs the first output voltage of the regulator as a second output voltage from the power supply circuit. A pre-charge circuit, connected to the regulator and the first switch circuit, generates the second output voltage from the input voltage before the first output voltage of the regulator is output as the second output voltage while controlling the first switch circuit.

Method and circuit for generating output voltages from input voltage

A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.

Method and circuit for reducing regulator output noise

A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C through C . A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C -C , ranging from the second left-most current source cell C to the second right-most current source cell C , are used as cyclically selected cells. The remaining left-most current source cell C and right-most current source cell C are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.

Method of selecting cells for input code in a digital-to-analog converter

It is an objective to provide a digital-to-analog converter circuit that allows the value of the current output from each current source cell to be identical, regardless of the position of that current source cell relative to the power supply line. To ensure that the voltages supplied to the respective current source cells are identical, the power supply lines La and Lb are disposed in the form of a right triangle modified such that their line widths W and W become constantly narrower on one side depending on the position at which the power supply lines La and Lb are formed. The power supply lines La and Lb are also disposed such that their hypotenuses are opposite to each other.

Digital-to-analog-converter

A digital-to-analog conversion circuit including a plurality of unit current output cells ( ) arranged in a matrix. Each of the current output cells ( ) includes a unit current source ( ) having a power supply input and a current output, and a selecting switch ( ) connected to the current output and having two switching output terminals. The circuit further includes at least one &frac12; and/or &frac14; weighted current output cell ( ) disposed on a row in the matrix, and at least one &frac12; and/or &frac14; supplementary current source ( ) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.

Digital-to-analog conversion circuit

An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.

Offset cancellation circuit

The A/D converter comprises a resistor series (30), a plurality of first comparators (1) and a plurality of second comparators (2). Resistor series (30) has a plurality of resistors(R) connected in series between two terminals to which predetermined reference voltages are applied. First comparator (1) compares a node voltage between resistors and an analog voltage signal to be compared. Second comparator (2) compares an average voltage of the two node voltages across each resistor R and the analog voltage signal. First and second comparators (1,2) are disposed alternatively.

Multi-bit A/D converter having reduced circuitry

A vertical contour correcting circuit that provides contour correction of a luminance signal at a horizontal color transition area of an image, thereby minimizing dot interference at the color transition area of a reproduced image. The vertical contour correcting circuit includes a vertical band-pass filter which outputs a level difference signal. The level difference signal is delayed to produce a first delay signal. The first delay signal is delayed to produce a second delay signal. An intermediate value signal is determined from the level difference signal, the first delay signal, and the second delay signal. The intermediate value signal and the first delay signal are added together so that their carrier color signal band components are canceled out.

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Sendai, Japan

Masami Aiura