Kabushiki Kaisha Toshiba

Ebara Corporation

Toshiba Memory Corporation

Other

Toshiba Electronic Devices & Storage Corporation

Masako Kodera

Atsushi Shigeta

Riichirou Aoki

Hiromi Yajima

Hiroshi Tomita

Norio Kimura

Hiroyuki Yano

Yoshitaka Matsui

Yukiteru Matsui

Shiro Mishima

Haruo Okano

Katsuya Okumura

Naoto Miyashita

Takeshi Nishioka

Koji Ono

Nobuo Hayasaka

Kenya Ito

Gaku Minamihaba

Tohru Watanabe

Tamami Takahashi

Rempei Nakata

Seiji Ishikawa

Yu Ishii

Soichi Nadahara

Hiroyuki Kawasaki

Masayoshi Hirose

Mitsuhiko Shirakashi

Toshiro Maekawa

Haruki Nojo

Katsuhiko Tokushige

Kenichi Nagaoka

Masami Watase

Masao Asami

Tetsuji Togawa

Kyoichi Suguro

Tomoko Matsudai

Masatoshi Yoshikawa

Minoru Amano

Yukio Ikeda

Motosuke Miyoshi

Noriaki Matsunaga

Seiji Katsuoka

Kunihiko Sakurai

Hideyuki Tomizawa

Akifumi Gawase

Motoyuki Sato

Toyomi Nishi

Masayoshi Iwayama

You Ishii

Tadayoshi Watanabe

Takashi Yoda

Riichiro Aoki

Hajime Eda

Satomi Hamada

Gisuke Kouno

Fumihiko Sakata

Yosuke Otsuka

Hiroshi Kosukegawa

Shirou Mishima

Motoaki Okada

A substrate processing apparatus removes foreign substances from a substrate at high removal efficiency. The substrate processing apparatus includes: a scrubber to perform surface processing of the substrate by bringing a scrubbing member into sliding contact with a first surface of the substrate, a hydrostatic support mechanism for supporting a second surface of the substrate via fluid pressure without contacting the substrate, the second surface being an opposite surface of the first surface, a cleaner to clean the processed substrate, and a dryer to dry the cleaned substrate. The scrubber brings the scrubbing member into sliding contact with the first surface while rotating the scrubbing member about a central axis of the scrubber.

Substrate processing apparatus and substrate processing method

A crystal analysis apparatus includes a first storage unit storing a crystal lattice image of a crystal region of a sample and a reference crystal lattice image for the crystal region of the sample. A first image processing unit is configured to generate a moir&#xe9; image from the crystal lattice image and the reference crystal lattice image. A second storage unit stores a predetermined correspondence relationship between a moir&#xe9; fringe pattern in the moir&#xe9; image and a crystal defect in the crystal region or a predetermined correspondence relationship between the moir&#xe9; fringe pattern in the moir&#xe9; image and a crystal strain in the crystal region. An analysis unit is configured to compare the moir&#xe9; fringe pattern in the moir&#xe9; image to predetermined correspondence relationships stored in the second storage unit.

Crystal analysis apparatus and crystal analysis method

According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography.

Method for fabricating semiconductor device

A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second electrode above the first semiconductor layer and electrically connected to the first semiconductor layer, a first insulating layer above the first semiconductor layer between the first and second electrodes, and a third electrode. The second electrode is spaced from the first electrode along the first semiconductor layer. The third electrode includes a first portion above the first insulating layer between the first and second electrodes, and a second portion between the first portion and the second electrode and extending from the first portion in the direction of, and spaced from, the second electrode. The distance between the first semiconductor layer and an adjacent curved surface of the second portion gradually increases from the first portion to the end of the second portion distal the first portion.

Semiconductor device

In a substrate processing method according to an embodiment, a surface of an object to be polished disposed on a substrate is polished on a polishing pad supplied with slurry. After the polishing process using the slurry, the surface of the object to be polished on the polishing pad is polished, while supplying water on the polishing pad where a residue including the slurry or a sludge of the polishing pad adhered. After the polishing process using the water, the surface of the object to be polished is cleaned on the polishing pad by supplying rinse liquid on the polishing pad.

Substrate processing method

According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.

Method for chemical planarization and chemical planarization apparatus

According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.

Semiconductor device and method of manufacturing the same

According to one embodiment, a polishing method comprises pressing a substrate being rotated against a polishing pad being rotated and supplying slurry on the polishing pad, measuring a surface temperature of the polishing pad, and when the surface temperature is not less than a predetermined temperature, jetting jet stream containing supercooled droplets from a nozzle having a narrow portion toward the polishing pad.

Polishing method and polishing apparatus

According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.

A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment.

Semiconductor device including a metal wiring with a metal cap

A method of manufacturing a semiconductor device, including the following processes of forming a structure in which a barrier metal containing at least of Ti and Ta and a copper wiring are exposed on its surface, or a structure in which at least one substance selected from the group consisting of Ti, W, and Cu and Al are exposed on its surface, above a semiconductor substrate, and supplying a hydrogen-dissolved solution dissolving hydrogen gas to the surface of the structure.

Method of manufacturing a semiconductor device using a wet process

A polishing apparatus is used for chemical mechanical polishing a copper (Cu) layer formed on a substrate such as a semiconductor wafer and then cleaning the polished substrate. The polishing apparatus has a polishing section having a turntable with a polishing surface and a top ring for holding a substrate and pressing the substrate against the polishing surface to polish a surface having a semiconductor device thereon, and a cleaning section for cleaning the substrate which has been polished. The cleaning section has an electrolyzed water supply device for supplying electrolyzed water to the substrate to clean the polished surface of the substrate while supplying electrolyzed water to the substrate.

Polishing method and apparatus

Provided is a method of manufacturing a semiconductor device, comprising preparing a base comprising a semiconductor substrate having a device surface side, a p-type semiconductor layer formed on the device surface side of the semiconductor substrate, a n-type semiconductor layer which is formed on the device surface side of the semiconductor substrate and forms a p-n junction together with the p-type semiconductor layer, and wirings formed above the semiconductor substrate and electrically connected to each other via the p-n junction, applying a chemical solution containing electrolytes to a device surface of the base, the wirings being exposed at the device surface of the base, and applying a liquid selected from the group consisting of anode water, oxidizing gas-dissolved water, radical-containing water, cathode water, reducing gas-dissolved water and an organic substance-adding solution to the device surface of the base.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, comprising the following processes of forming a structure in which a barrier metal containing at least of Ti and Ta and a copper wiring are exposed on its surface, or a structure in which at least one substance selected from the group consisting of Ti, W, and Cu and Al are exposed on its surface, above a semiconductor substrate, and supplying a hydrogen-dissolved solution dissolving hydrogen gas to the surface of the structure.

Growing community of inventors

Yokohama, Japan

Masako Kodera