Denso Corporation

Denso Corpora Tion

Masakiyo Sumitomo

Shigeki Takahashi

Tetsuo Fujii

Tsuyoshi Yamamoto

Hitoshi Yamaguchi

Nozomu Akagi

Yasushi Higuchi

Shigemitsu Fukatsu

Yoshiyuki Hattori

Shoji Mizuno

Hiroki Nakamura

Makoto Asai

Jun Sakakibara

Makoto Kuwahara

Yasuhiro Kitamura

Rie Taguchi

Hirotaka Saikaku

Koichi Murakawa

Yuu Yamahira

Yukihiro Kato

Tetsuya Matsuoka

Kazuma Fukushima

Noriyuki Kakimoto

Tomofusa Shiga

Akifumi Araragi

Yuma Kagata

Masanori Miyata

Takeshi Inoue

Masahiro Ogino

Weitao Cheng

Hiroto Sugiura

Tasbir Rahman

Shuichi Toriyama

A semiconductor device includes a main element and a sense element. Each of the main element and the sense element includes a drift layer, a base layer, an emitter region, a gate insulation film, a gate electrode, and a rear surface layer. The base layer is on the drift layer. The emitter region is at a surface layer portion of the base layer. The gate insulation film is disposed at a surface of the base layer between the emitter region and the drift layer. The gate electrode is on the gate insulation film. The rear surface layer faces the base layer with the drift layer between the rear surface layer and the base layer. The rear surface layer in the main element includes a collector layer. The rear surface layer in the sense element includes a low-impurity layer having smaller amount of impurities than the collector layer.

Semiconductor device

A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.

In a semiconductor device in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed to a semiconductor substrate, a plurality of carrier injection layers electrically connected with a second electrode and configuring a PN junction with a field stop layer is disposed in a cathode layer. When an impurity concentration of the field stop layer is defined as Nfs [cm], and a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L[&#x3bc;m], the plurality of carrier injection layers satisfies a relationship of L&#x3e;6.8&#xd7;10&#xd7;Nfs+20.

Semiconductor device including carrier injection layers

In a power converter, a control circuit has a speed adjustment resistor that limits a control current to adjust a switching speed of each of first and second switching elements. The speed adjustment resistor has a resistance that varies depending on a voltage at the control electrode of each of the first and second switching elements. A feedback route connects between the control electrode of the first switching element and the control electrode of the second switching element. The feedback route has a resistance that is set to be lower than a value of the resistance of the speed adjustment resistor during a predetermined Miller period of each of the first and second switching elements.

Power converter with switching elements, control circuit having speed adjustment resistor, and feedback route

In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.

A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.

A semiconductor device includes a drift layer, a base layer, a collector layer, gate insulating films, gate electrodes, an emitter region, a first electrode and a second electrode. The base layer is provided on the drift layer. The drift layer is provided between the base layer and the collector layer. The gate insulating films are respectively provided on wall surfaces of trenches penetrating the base layer to reach the drift layer. The gate electrodes are respectively provided on the gate insulating films. The emitter region is provided in a surface layer portion of the base layer, and is in contact with the trenches. The first electrode is electrically coupled with the base layer and the emitter region. The second electrode is electrically coupled with the collector layer. Some gate electrodes are applied with a gate voltage. Other gate electrodes are electrically coupled to the first electrode.

A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.

Semiconductor device and manufacturing method of the same

A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 &#x3bc;m.

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector layer on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and the carrier storage layer and reaching the drift layer; a gate electrode on an insulation film in each trench; and an emitter region in a surface portion of the base layer contacting each trench. A thickness of at least a portion of a part of the gate insulation film on a sidewall of each trench on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film on the sidewall of an opening portion side of the trench from the peak position.

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Semiconductor device having switching element and free wheel diode and method for controlling the same

A semiconductor device includes a first conductivity-type drift layer, a second conductivity-type base layer formed in a front surface portion of the drift layer, a second conductivity-type collector layer formed in the drift layer and separated from the base layer, gate insulation layers formed on a surface of the base layer, gate electrodes individually formed on the gate insulation layers, an emitter layer formed in a front surface portion of the base layer, an emitter electrode electrically connected to the emitter layer and the base layer, and a collector electrode electrically connected to the collector layer. A rate of change in a gate voltage of a part of the gate electrodes is smaller than a rate of change in a gate voltage of a remainder of the gate electrodes. The emitter layer is in contact with only the gate insulation layers provided with the part of the gate electrodes.

In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.

Trench-gate-type insulated gate bipolar transistor

In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L(&#x3e;0) of the ineffective region in the y-direction, a length Dof the communication portion in the z-direction, and a length Dof the bottom portion in the z-direction satisfy L&#x2266;2(D+D). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.

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Okazaki, Japan

Masakiyo Sumitomo