Kabushiki Kaisha Toshiba

Masaki Unno

Masanobu Shirakawa

Hiroshi Sukegawa

Tokumasa Hara

Naoya Tokiwa

Toshio Fujisawa

Shirou Fujita

A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store.

High performance semiconductor memory device that has different page addresses allotted to multiple bits of memory cells

According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.

Semiconductor memory device

Growing community of inventors

Kanagawa, Japan

Masaki Unno