Fujitsu Corporation

Masaki Ukai

Takashi Suzuki

Aiichiro Inoue

Hiroyuki Kojima

Tomoyuki Okawa

Megumi Yokoi

Hideyuki Unno

Toshio Yoshida

Ryuichi Sunayama

Hideki Sakata

Kumiko Endo

Shuichi Yoshizawa

Kyoko Tashima

Naohiro Kiyota

Daisuke Itou

Yuji Shirahige

Tsuyoshi Motokurumada

Souta Kusachi

Naozumi Aoki

Matthew Depetro

Mie Tonosaki

Kuniki Morita

Susumu Akiu

Aiichirou Inoue

An arithmetic operation unit includes: a first multiplier configured to multiply two first input data to calculate first arithmetic data; a second multiplier configured to multiply two second input data to calculate second arithmetic data; a first adder configured to add the first arithmetic data and the second arithmetic data to calculate third arithmetic data; a first arithmetic selector configured to select one of the first arithmetic data and the third arithmetic data; a second arithmetic selector configured to select one of the second arithmetic data and the third arithmetic data; a second adder configured to add third input data and arithmetic data selected by the first arithmetic selector to calculate first arithmetic result data; and a third adder configured to add input fourth data and arithmetic data selected by the second arithmetic selector to calculate second arithmetic result data.

Arithmetic operation unit and method of controlling arithmetic operation unit

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full

A data processing system is provided. The data processing system includes a plurality of processors, a cache memory shared by the plurality of processors, in which memory a cache line is divided into a plurality of partial writable regions. The plurality of processors are given exclusive access rights to the partial writable region waits.

Data processing system and cache control method

An error judging circuit includes a first EOR circuit tree that generates a check bit of a correction code by polynomial remainder calculation with respect to a polynomial expression of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2) in SEC-DED using Reed-Solomon code, a second EOR circuit tree for generating syndromes from S=Y(&#x3b1;) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is to be detected an error and has a possibility that an error is mixed is Y(x), and an error detection circuit unit that detect if there is a one block error, a two block error, or no error based on whether or not an equation of syndromes S=SSis satisfied.

Error judging circuit and shared memory system

A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.

Cache controller and cache control method

A transmitting side device () and a receiving side device () are connected to each other via a bus () comprising TAG bits (), data bits () and error detection/correction ECC bits (). The transmitting side device () uses a redundant bit inversion circuit () to invert different bits of the ECC bits () corresponding to trigger signals (&). In the receiving side device (), a determination circuit (), which has received an error report signal () from an error detection/correction circuit (), determines, from the position of an error bit in the ECC bits (), which one of the trigger signals (&) has been transmitted from the transmitting side device ().

Control method of information processing device and information processing device

The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Processor for controlling tread switching

To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage datastored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG.(). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data(for example, entry) from the LRU information as a candidate for the LRU control, based on the storage dataas the ID of the entry with the oldest last use time.

Method for updating information used for selecting candidate in LRU control

A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Method and apparatus for controlling degradation data in cache

A plurality of system controllerseach comprising a memory mediumand an I/O deviceunder the control of the system controllerare connected to a CPU nodeby way of a plurality of system buses. The CPU nodeexecutes a memory interleave for distributing memory accesses to the system buses(i.e., the system controllers). In performing an I/O access to the I/O device, the CPU nodefirstly inquires from a representative system controller(SC) as to which system bus(i.e., a system controller) has a target I/O deviceand then executes an actual I/O access to the system busreturned in a response from the SC. Even when the CPU nodeexecutes a memory interleave in the case of a memory-mapped I/O, the CPU nodeis not required to manage the location information of the I/O device

Central processing apparatus, control method therefor and information processing system

A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.

Barrier synchronization method, device, and multi-core processor

A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.

Coherency maintaining device and coherency maintaining method

Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline.

Recording controller and recording control method

Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.

Branch prediction table storing addresses with compressed high order bits

An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return address stack by, changing the designate entry to indicate a one-step shallower entry when a call instruction is predicted during the instruction fetching, changing the designate entry independently of a push or pop operation to indicate a one-step deeper entry when a return instruction is predicted during an instruction fetching, and changing the designate entry depending upon a push and a pop operation when a call and return instruction is completed, thereby keeping a position of the designate entry. The entry designation unit designates an entry as predicted return address of a subroutine when the fetched instruction hitsin a branch history and determined as a return instruction.

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Kawasaki, Japan

Masaki Ukai