Mitsubishi Electric Corporation

Masaki Ueno

Kinya Yamashita

Akira Okada

Yasushi Takaki

Takaya Noguchi

Masayoshi Hirao

Reona Furukawa

According to the present disclosure, a semiconductor manufacturing apparatus comprises a pickup stage having a mechanism for lifting and lowering a semiconductor chip having a square shape. The pickup stage comprises first pushing-up blocks at four corners. Each of the first pushing-up blocks comprises a first side parallel to one side of the semiconductor chip, a second side parallel to another side of the semiconductor chip, and an offset portion formed between the first side and the second side to be offset to an inward side of an intersection point of respective extension lines of the first side and the second side.

Semiconductor manufacturing apparatus

An input capacitance measurement circuit includes a transformer, a first capacitor, a second capacitor, and a third capacitor. A primary wire of the transformer has a first end provided so as to be connectable to an anode of the semiconductor device. The primary wire of the transformer has a second end connected to a first end of the first capacitor. A secondary wire of the transformer has a first end provided so as to be connectable to a cathode of the semiconductor device. The secondary wire of the transformer has a second end connected to a first end of the second capacitor. The third capacitor has a first end provided so as to be connectable to the cathode of the semiconductor device. A second end of the first capacitor, a second end of the second capacitor, and a second end of the third capacitor are electrically connected to each other.

Input capacitance measurement circuit and method of manufacturing semiconductor device

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

Semiconductor test apparatus and semiconductor test method

An evaluation apparatus includes an insulating plate, a plurality of probes fixed to the insulating plate, an insulating portion having a connection portion connected to the insulating plate in a detachable manner and a tip portion continuous with the connection portion, the tip portion being narrower than the connection portion, an insulator formed by combining the insulating portions to surround the plurality of probes in planar view, and an evaluation unit for passing currents through the plurality of probes to evaluate electrical characteristics of an object to be measured.

Evaluation apparatus including a plurality of insulating portions surrounding a probe and semiconductor device evaluation method based thereon

Provided is a technique capable of preventing occurrence of partial discharge. An evaluation apparatus includes a probe disposed on an undersurface of an upper component; a sidewall part disposed on the undersurface of the upper component and enclosing sides of the probe; and a first gas supplying part. The first gas supplying part is capable of supplying a gas to a to-be-measured object that is placed on a stage when the sidewall part comes in proximity to the stage, and to a space enclosed by the stage, the sidewall part, and the upper component when the sidewall part is in contact with the stage.

Growing community of inventors

Tokyo, Japan

Masaki Ueno