Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Mitsubushi Denki Kabushiki Kaisha

Renesos Technology Corp.

Masaki Tsukude

Kazutami Arimoto

Kazuyasu Fujishima

Tsukasa Ooishi

Hirotoshi Sato

Yoshio Matsuda

Takafumi Takatsuka

Mikio Asakura

Shigeki Tomishima

Hideto Hidaka

Tadato Yamagata

Tadayuki Shimizu

Shinichi Kobayashi

Fukashi Morishita

Masanori Hayashikoshi

Ryu Makabe

Shinji Tanaka

Yuichiro Ishii

Takahiro Tsuruda

Yoshikazu Saito

Katsuhiro Suma

Shinji Kawai

Minoru Senda

Takeshi Hamamoto

Tetsushi Tanizaki

Shigehiro Kuge

Teruhiko Amano

Tsukasa Hagura

Yasuhiko Tsukikawa

Takeshi Fujino

Kyoji Yamasaki

Yoshito Nakaoka

Yukinobu Adachi

Yasuhiko Nitta

Tsukasa Oishi

Tsukasa Ohishi

A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

Semiconductor memory device and test method therefor

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.

A semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively.

Semiconductor device

A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

Semiconductor memory device suitable for mounting on portable terminal

Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.

Semiconductor memory device

This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.

In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an 'H' level and then reset to an 'L' level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an &#x201c;H&#x201d; level and is not reset to an &#x201c;L&#x201d; level while the corresponding upper address is designated. This can reduce the standby current.

Semiconductor memory device having complete hidden refresh function

The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.

Semiconductor device having internal power supply voltage generation circuit

A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Fully-hidden refresh dynamic random access memory

In a freeze reset circuit in a semiconductor memory device, when a row act signal is not activated in a predetermined period determined by a trailing edge delay circuit after a chip enable signal is set to the H level during a write or read operation, a freeze reset signal is output from a logic gate after a predetermined period. As a result, the semiconductor memory device terminates the write or read operation. Therefore, the semiconductor memory device can ensure the stability of the write or read operation.

Semiconductor memory device having control circuit

Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

Fully hidden refresh dynamic random access memory

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Hyogo, Japan

Masaki Tsukude