Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Masaki Toyokura

Toshiyuki Araki

Kunitoshi Aono

Yoshifumi Matsumoto

Kiyoshi Okamoto

Hisashi Kodama

Shiro Sakiyama

Takashi Akiyama

Akihiro Watabe

Masakatsu Maruyama

Akihiko Ohtani

Masahiro Gion

Hiroshi Imanishi

Masayuki Taniyama

Yoshinori Okajima

Masahiro Takeuchi

Shun-ichi Kurohmaru

Takuya Jinbo

Akihiro Otani

Disclosed herein is a semiconductor integrated circuit which controls the quality of an image and includes a viewer detector, a region specifier, and a controller. The viewer detector detects the number of viewer(s) watching the image and a gaze region being watched by the viewer within the image. If the number of viewers is plural, the region specifier specifies a local region of the image as a target region based on a plurality of gaze regions being watched by the viewers. The controller performs image quality control on the target region.

Semiconductor integrated circuit, display device provided with same, and control method

A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.

Bus controller

When an input picture is inputted to a video interface and stored in a reordering memory, the input time is recorded utilizing a reference time generator and a frame sync signal, and a frame memory to be encoded by an encoding unit is designated using the time information. Therefore, an encoder, which can perform stable encoding even when intervals of vertical sync signals are varied, is realized.

Video encoding apparatus, video encoding method, and frame rate conversion apparatus

A variable-length code decoder sequentially decodes a series of variable-length codewords included in a bit stream and outputs decoded symbols corresponding to the codewords. The decoder includes an interface section and a decoding section. The interface section accumulates various code lengths of the decoded codewords to obtain a sum. Next, the interface section selects an N-bit contiguous data sequence (where N is a maximum code length of the codewords) from a 2N- or (2N&minus;1)-bit contiguous data sequence, included in the bit stream, in accordance with the sum and outputs the N-bit contiguous data sequence. The decoding section receives the output of the interface section and decodes a codeword included in a combination of the output and a previous output of the interface section by reference to a lookup table, thereby obtaining and outputting a decoded symbol and outputting a code length of the decoded codeword to the interface section.

Variable-length code decoder using barrel shifters and a look-up table

In an animation encoding process, a motion vector which can minimize an AC component included in a discrete cosine transform result is detected. For this purpose, a block X (i, j) to be processed is extracted from an input image X, and a prospective reference block Y,(i, J) is extracted from a reference image Y, wherein k is an integer depending upon the size of a motion vector search range, i&equals;0, . . . , or 3, and j&equals;0, . . . , or 63. From each pixel value in each sub block (including 8&times;8 pixels) of the block to be processed, an average value X,(i) of pixels in the sub block is subtracted, and from each pixel value in each sub block (including 8&times;8 pixels) of the prospective reference block, an average value Y,(i) of pixels in the sub block is subtracted. Then, an evaluation value S,for block matching is calculated. The prospective reference block having the minimum evaluation value is selected as a reference block among the plural prospective reference blocks, so as to obtain a motion vector V corresponding to the positional relationship between the block to be processed and the reference block.

Motion vector detecting circuit

The present invention makes it possible to achieve restoration of decoding processing more intricately in comparison with commonly-used techniques. The present invention increases post-restoration data reliability and is applicable to real-time decoding processing. A variable length code converter of the present invention provides an abnormal code detection signal when a bit-string subjected to conversion corresponds to none of variable length codes that belong in predetermined coding systems. At this time, a controller provides an error signal, and according to the error signal a bit-string is continuously output from a memory which stores bit-strings to be decoded. When the controller detects a header indicative of data partition from an output bit-string of the memory, it cancels the error signal. As a result, bit-string decoding resumes after the detected header.

Code converter, variable length code decoder, and associated methods

Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.

Orthogonal transform processor

The two-dimensional DCT (discrete cosine transform) of plural n.times.n data items is carried out at high speed, with requiring less hardware. X(h) is an operation in which row vectors of A(h) are sequentially transmitted from a first memory to a one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding row vectors of B(h) of a second memory. Y(h) is an operation in which column vectors of B(h) are sequentially transmitted from the second memory to the one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding column vectors of C(h) of the first memory. The operation X(h) starts at h=1 and ends at h=m. Then, the operation Y(h) starts at h=1 and ends at h=m. The one-dimensional DCT processor performs the pipelining operation of n-element one-dimensional vectors for product-of-matrices computations.

Two-dimensional orthogonal transform processor

A subtracter performs a subtraction (Xi-Yi) per corresponding components of two pairs of N-dimensional vector data (X1, X2, . . . XN), (Y1, Y2, . . . , YN). An exclusive disjunction circuit selects (Xi-Yi) when a result of subtraction is positive, and inverts bits of the result of subtraction to select the bit-inverted data (Xi-Yi) when the result of subtraction is negative. The selection is carried out using a most significant bit of the result of subtraction as a control signal. An accumulator accumulates the selected data and a value of the most significant bit of the result of subtraction. Accordingly only one subtracter suffice. Since the operation of adding 1 to the inverted data of the result of subtraction when the result of subtraction is negative is carried out concurrently with the accumulation of the result of subtraction by the accumulator, a vector correlation detecting circuit with less element and reduced operation time is contemplated.

Vector correlation detecting circuit

The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.

Digital processor capable of concurrently executing external memory

The output of a butterfly unit is entered into a product-sum unit in a forward DCT and the output of the product-sum unit is entered into the butterfly unit in an inverse DCT. The product-sum unit employs, as a bit-string distribution circuit, a register circuit having eight bit shift registers each having a 16-bit parallel input and a 2-bit shift output and the bit shift registers are different in bit width from one another. Data are entered into the bit shift registers with the largest bit-width bit shift register first, such that the respective bit shift registers are shifted rightward by 2 bits per cycle. Four shift registers are disposed between the bit-string distribution circuit and a RAG circuit such that, when bit strings are entered, as delayed cycle by cycle, into eight RAGs of the RAC circuit, the final accumulation results are successively provided from the RACs in a proper order. This reduces the bi-directional DCT processor in circuit arrangement.

Two sets of input data A and B are provided. A first selector circuit outputs either the most significant bit of the input data B or the inversion thereof, in accordance with a control signal which has been sent thereto through a control line. An adder adds 1 to the least significant bit of the input data B, and also adds the output from the first selector circuit to all the other bits thereof. A zero-judgment circuit judges whether the input data B is 0 or not, and then, if it is 0, sets a flag to a predetermined value. A selector-control circuit allows a second selector circuit to select the input data B in the case where the least significant bit of the input data A is 1 or the flag from the zero-judgment circuit is set to the predetermined value, and to select, in the other cases, the output from the adder. In this manner, a conditional branch operation required for quantization and inverse quantization of data is executed at high speed, which operation involves either adding 1 to or subtracting 1 from the input data B to output the result, or outputting the input data B, depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number.

Arithmetic unit for quantization/inverse quantigation

In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.

Program control type vector processor for executing a vector pipeline

A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

Multidimensional address generator and a system for controlling the

A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

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Osaka, Japan

Masaki Toyokura