Panasonic Corporation

Socionext Inc.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Pansonic Corporation

Masaki Tamaru

Kazuyuki Nakanishi

Hidetoshi Nishimura

Tomoaki Ikegami

Hideaki Kondo

Hiroki Taniguchi

Ritsuko Ozoe

Shinzo Koyama

Nana Okamoto

Shigetaka Kasuga

Kazuma Yoshida

Hiroyuki Shimbo

Toshiyuki Moriwaki

Tetsuyuki Fukushima

Tatsuya Kabe

Hiroshi Koshida

Michiya Otsuji

Takashi Andoh

A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

A solid-state imaging apparatus includes a plurality of pixel circuits arranged in a matrix. Each pixel circuit includes: a photodiode; a first charge storage that stores a charge; a floating diffusion region that stores a charge; a second charge storage that stores a charge; a first transfer transistor that transfers a charge from the photodiode to the first charge storage; a second transfer transistor that transfers a charge from the first charge storage to the floating diffusion region; a first reset transistor that resets the floating diffusion region; and an accumulating transistor for accumulating a charge of the floating diffusion region in the second charge storage. The capacitance of the first charge storage is greater than the capacitance of the floating diffusion region, and the capacitance of the second charge storage is greater than the capacitance of the floating diffusion region.

Solid-state imaging apparatus and ranging apparatus

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

Semiconductor device

A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array

A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.

Semiconductor device including a local wiring connecting diffusion regions

In a layout structure of a standard cell including off transistorsunnecessary for logic operation of a circuit, dummy via contactsare disposed on impurity diffusion regionsof the off transistors, respectively. Dummy metal interconnectsare connected to the dummy via contacts, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit

A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Growing community of inventors

Kyoto, Japan

Masaki Tamaru