Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Power Semiconductor Device, Ltd.

Hitachi, Ltd.

Hitachi Astemo Ltd.

Masaki Shiraishi

Nobuyoshi Matsuura

Tomoaki Uno

Yukihiro Satou

Takayuki Hashimoto

Noboru Akiyama

Tetsuya Kawashima

Mutsuhiro Mori

Takayuki Iwasaki

Toshio Nagasawa

Tomoyasu Furukawa

Kozo Sakamoto

Tomoyuki Miyoshi

So Watanabe

Takashi Hirao

Hiroshi Suzuki

Yujiro Takeuchi

Yoshito Nakazawa

Atsuo Watanabe

Akihiro Miyauchi

Tetsuya Ishimaru

Toshiaki Morita

Koji Tateno

Junichi Sakano

Koichi Yahata

Takasumi Ohyanagi

Shinichi Kurita

Yosuke Inoue

Shigeo Tokumitsu

Yohihiro Satou

Tetsuo Oda

Yutaka Kato

A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

Semiconductor device and power conversion device

Provided is a highly reliable semiconductor device in which an influence on device characteristics can be reduced while improving a high temperature and high humidity bias resistance of a termination structure (termination region) of a chip by a relatively simple method. The semiconductor device includes an active region disposed on a main surface of a semiconductor substrate, and a termination region disposed on the main surface so as to surround the active region. The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate, and an organic protective film formed so as to cover the interlayer insulating film. An insulating film having a thickness of 100 nm or less and containing nitrogen is provided between the interlayer insulating film and the organic protective film.

Semiconductor device and termination structure

A semiconductor element drive device is provided to solve a problem that because a case of a change in the temperature of the semiconductor element or a current flowing through the semiconductor element is not take into consideration, switching loss and noise cannot be reduced sufficiently. In accordance with input sensing information (temperature T, current I), a timing control unitoutputs a delay signal Q to control timing of driving a current increasing circuitso that a reduction of switching loss of an IGBTis maximized. When the IGBTis in turn-on mode or turn-off mode, the current increasing circuitoutputs a drive signal in response to the delay signal Q delayed by a given time from output of the drive instruction signal P. In this way, the current increasing circuitincreases the current that causes the gate capacitor of the IGBTto be charged/discharged in response to the delay signal Q, thereby increasing a switching speed to reduce switching loss.

Semiconductor element drive device and power conversion apparatus

A current switching semiconductor device to be used in a power conversion device achieves both a low conduction loss and a low switching loss. The semiconductor device includes the IGBT in which only Gc gates are provided and an impurity concentration of the p type collector layer is high, and the IGBT in which the Gs gates and the Gc gates are provided and an impurity concentration of the p type collector layer is low. When the semiconductor device is turned off, the semiconductor device transitions from a state in which a voltage lower than a threshold voltage is applied to both the Gs gates and the Gc gates to a state in which a voltage equal to or higher than the threshold voltage is applied to the Gc gates prior to the Gs gates.

The invention provides an inexpensive flywheel diode having a low power loss. A semiconductor substrate side of a gate electrode provided on a surface of an anode electrode side of a semiconductor substrate including silicon is surrounded by a p layer, an n layer, and a p layer via a gate insulating film. The anode electrode is in contact with the p layer with a low resistance, and is also in contact with the n layer or the p layer, and a Schottky diode is formed between the anode electrode and the n layer or the p layer.

A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.

Semiconductor device and alternator using the same

Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions.

Semiconductor device and power conversion apparatus

In a non-insulated DC-DC converter having a circuit in which a power MOS&#x22c5;FET high-side switch and a power MOS&#x22c5;FET low-side switch are connected in series, the power MOS&#x22c5;FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS&#x22c5;FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS&#x22c5;FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Semiconductor device with first and second chips and connections thereof and a manufacturing method of the same

In a non-insulated DC-DC converter having a circuit in which a power MOS&#x2022;FET high-side switch and a power MOS&#x2022;FET low-side switch are connected in series, the power MOS&#x2022;FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS&#x2022;FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS&#x2022;FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS&#x2022;FET for a high side switch and a power MOS&#x2022;FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor device including a DC-DC converter

Semiconductor device including DC-DC converter

A semiconductor device includes first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is formed near a surface of the first semiconductor layer; a first main electrode that is electrically connected to the second semiconductor layer; a third semiconductor layer of the second conductivity type that neighbors the first semiconductor layer; a fourth semiconductor layer of the first conductivity type that is selectively disposed in an upper portion of the third semiconductor layer; a second main electrode that is electrically connected to the third semiconductor layer and the fourth semiconductor layer; a trench whose side face is in contact with the third semiconductor layer and the fourth semiconductor layer; a gate electrode that is formed along the side face of the trench by a sidewall of polysilicon; and a polysilicon electrode.

Semiconductor devices and power conversion systems

Semiconductor device and a manufacturing method of the same

Growing community of inventors

Hitachi, Japan

Masaki Shiraishi