Mitsubishi Denki Kabushiki Kaisha

Masaki Shimoda

Hideshi Miyatake

Kazuhiro Tsukamoto

Hiroyuki Yamasaki

Hideto Hidaka

Katsumi Dosaka

Yasuhiro Konishi

Masaki Kumanoya

Yuto Ikeda

Yoshinori Inoue

In a slew rate adjusting circuit for producing a timing signal determining an output slew rate, a delay circuit for producing an output timing signal is formed of delay circuits with a variable number of delay stages, and the delay time of the output timing signal is adjusted in a step of a delay time of the delay stage in accordance with slew rate adjusting data. A large adjustment margin can be ensured for the output slew rate determining the changing rate of the output data.

Slew rate adjusting circuit and semiconductor device

A semiconductor device with more scale reduction and without restriction of arrangement of connection pads for preventing them from being covered is obtained. The semiconductor device has first and second semiconductor chips stacked on a substrate, wherein a connection pad of the first semiconductor chip faces the substrate, and the first and second semiconductor chips are both connected to input/output terminals of the substrate by means of wires.

Semiconductor device

There are provided upper and lower data I/O terminal groups, each forming a unit for input/output of data. When an early write detecting circuit included in a clock generating circuit detects designation of an early write mode and one of the groups is designated for writing, lower or upper input buffers controlled by write control circuit takes in the data. Concurrently, in response to the detection of mode, lower or upper output buffer uses, for reading, the other group not taking in data for writing. In this mode, therefore, the write and read operations are executed simultaneously. Thereby, simultaneous operation of the write and read data is allowed, and a data processing speed is improved.

Semiconductor memory device having a plurality of I/O terminal groups

A transfer gate is provided between an input terminal, receiving voltage Vh of the super Vcc level when a special operating mode is set, and an inverter and an n channel MOS transistor included in a super Vcc detection circuit of a DRAM. The transfer gate is rendered conductive only during a potential detection period during which signal WCBR attain an 'H' level. Therefore, a leakage current flowing from the input terminal through the n channel MOS transistor to a ground terminal can be minimized, thereby reducing a consumed current.

Super VCC detection circuit

A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

Block partitioned dynamic semiconductor memory device

A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

Semiconductor memory device with address transition detection and timing

A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals '0'. The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals '1'. A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

Redundary circuit with a spare main decoder responsive to an address of

A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Growing community of inventors

Hyogo, Japan

Masaki Shimoda