Nec Electronics Corporation

Ricoh Company, Ltd.

Asahi Kogaku Kogyo Kabushiki Kaisha

Nec Corporation

Renesas Electronics Corporation

Dwango Co., Ltd.

Masaki Sano

Yoshiaki Hanyu

Hitomi Kumazaki

Kan Tomita

Takashi Sato

Hajime Hoshi

Hidetaka Yokota

Kinji Kayanuma

Norimichi Takahashi

Hiroki Kubozono

Naomi Inoue

Akihiko Koizuka

Akira Ohori

Kenchi Miyazaki

Nobuharu Takahashi

In the conventional technology, a flag, which is for processing non-display of a certain comment according to existence or number of counts of deletion requests, is given to the comment in server side and distributed to the respective terminals. Therefore, there is a deficiency that comments with flags are not displayed in all users' terminals without exception. In order to solve the above deficiency, the present invention provides a comment distribution system, where a score is given to a comment to be distributed, the score is reduced in the distribution server according to registrations of inappropriate word from users as viewers, and a threshold is given with respect to each reproduction terminal and the score and the threshold are compared, thereby determining whether the comment is reproduced.

Comment distribution system, and a method and a program for operating the comment distribution system

A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.

PLL circuit and optical disc apparatus

A multiphase clock with high resolution is generated. A first clock generator circuit () includes n level converters BUFs that conduct level conversion on two input signals, and generate a pair of pulse signals that switch the levels with reference to a crossing point at which the two signal are identical in level with each other. An i-th BUF in the first clock generator circuit () inputs a one-side output pair that is respective one-side outputs of the differential outputs of two i-th (1&#x2266;i&#x2266;n) and (i+1)-th (1 when i=n) differential circuits in a ring oscillatorin which n differential circuits DCELs having differential inputs and outputs are connected in a ring configuration. The one-side output pair is two one-side outputs that are input to the noninverting terminal of the next differential circuit, or the two one-side outputs that are input to the inverting terminal of the next differential circuit.

Clock generator

A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

VCO circuit, PLL circuit using VCO circuit, and data recording apparatus the PLL circuit

A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

Phase locked loop circuit including digital voltage-controlled oscillator, ring oscillator and selector

Disclosed is a PLL circuit having a voltage-controlled oscillator, to which a difference voltage across non-inverting and inverting input terminals is input as a control voltage, for oscillating at a frequency in accordance with the control voltage; a phase comparator for comparing the phase of an output signal obtained by frequency-dividing the output of the voltage-controlled oscillator by a frequency-divider, with the phase of an input signal and outputting the result of this phase comparison; first and second loop filters connected at output terminals thereof to the non-inverting and inverting input terminals, respectively, of the voltage-controlled oscillator; and a charge pump, which is responsive to receipt of an UP signal supplied from the phase comparator, for supplying a first charging current from a PMOS transistor to a capacitor of the first loop filter and supplying a first discharge current from an NMOS transistor to a capacitor of the second loop filter, and which is responsive to receipt of a DOWN signal supplied from the phase comparator, for supplying a second charging current from a PMOS transistor to a capacitor of the second loop filter and supplying a second discharge current from an NMOS transistor to a capacitor of the first loop filter.

PLL circuit and data read-out circuit

A PLL circuit for comparing with a phase comparatorphase between an input signal and one of multiphase pulse signals CKDIV to CKNDIV used as a channel clock generated by an output of a controlled oscillator, and controlling an oscillation of the controlled oscillatoraccording to a phase difference signal, comprises a frequency fixing circuitfor outputting an activating signal PCSTART for the control when the input signal is nearly equivalent to a frequency of the channel clock and has entered into a capture range of the phase comparator and a selection circuitfor selecting as the channel clock a multiphase pulse signal of a closest phase to a generating point of the input signal after generation of the activating signal, and the selection circuitdecides whether the input signal is advanced or delayed with respect to the channel clock after having selected a multiphase pulse signal as the channel clock and generates either an advance signal or delay signal according to the advance/delay of the input signal, for controlling a skew adjusting circuitwith the advance signal or delay signal.

PLL circuit and phase difference detecting circuit that can reduce phase pull-in time and adjust a skew at a higher precision

A phase locked loop has a charge pump circuit connected through a loop filter to a voltage controlled oscillator, and the charge pump circuit is controlled by a frequency/phase comparator, wherein the charge pump circuit includes a first current mirror circuit responsive to a first control signal for regulating a discharging current from the loop filter to a first target amount proportional to a constant current, a second current mirror circuit for regulating a reference current to a second target amount proportional to the constant current and a third current mirror circuit responsive to a second control signal for regulating a charging current to the loop filter to a third target amount proportional to the reference current, a first switching circuit for charging a first parasitic capacitor coupled to the first current mirror circuit from the constant current source and a second switching circuit for charging a second parasitic capacitor coupled to the third current mirror circuit through the second current mirror circuit, thereby setting a limit on a spike current generated at a change of the first and second control signals.

Charge pump circuit for phase locked loop free from spike current

A graphics processing apparatus carries out an antialiasing for obtaining an output image having smooth edges, enabling a speedy computation of approximate shading area rates of pixels by making use of neither a subpixel dividing process nor a shading pixel counting process. The apparatus comprises a discriminating part for discriminating the presence of an end point pixel at an edge portion of an image defined by a vector data, a computing part for computing the number of edge pixels by extracting two integer parts a, b from x coordinate values Xa, Xb of two points where a scanline intersects the vector data, a setting part for setting a x coordinate value of the end point pixel to the Xb only when an end point pixel is found at the edge portion, an approximate point part for determining an approximate point value C' from a prescribed factor c.times.(n-1) computed by a decimal fraction c extracted from the x coordinate value Xa, a memory part for storing a lookup table containing a set of predetermined data, and an approximate area factor part for determining an approximate shading area factor k by making reference to the lookup table stored in the memory part.

Graphics processing apparatus for producing output data at edges of an

A flexible printed circuit board is provided including a flexible sheet having at least one electrically conductive layer, with a printed circuit pattern and a fold retainer pattern formed in one of the electrically conductive layers. The fold retainer pattern is electrically isolated from the printed circuit pattern. The fold retainer pattern has notches that indicate where the sheet is to be folded when the flexible sheet is folded, it is held in its folded shape by the fold retainer pattern.

Flexible printed circuit board

A graphics processing apparatus includes a first detection part for detecting, with respect to each pixel of an image, whether or not an edge of the image starts on a scanline, and for setting a control data depending on whether or not the edge starts on the scanline, a second detection part for detecting a duration of beam power modulation corresponding to one or plural edge pixels being intersected by a line defined in the image, and for setting a duration data, a third detection part for detecting an outermost edge pixel in the edge pixels, a part for generating a beam power data indicating an intensity level of light beam power corresponding to the outermost edge pixel, an output part for outputting the image by means of a printer having a light source for emitting a light beam, and a control means for continuously modulating light beam power of the light source from the intensity level to a predetermined level with respect to the edge pixels, so that an image with smooth edges is generated by modulating the light beam power of the light source in accordance with the control data and the duration data.

Graphics processing apparatus for smoothing edges of images

A graphic output device for removing the aliases of the edges of a vector image by an antialiasing procedure and effectively outputting image data undergone such processing. Whether or not the inclination of an input vector is greater than 45 degrees is determined. In the event of outputting the result of antialiasing processing, a pulse width modulation system (vertically long dot diameter) is selected if the inclination of the vector is greater than 45 degrees, or a power modulation system (horizontally long dot diameter) is selected if it is smaller than 45 degrees.

Graphic output device including antialiasing capability governed by

A liquid crystal display panel is housed in a frame and has a first group of leads disposed on an edge thereof. The frame is supported on a printed-circuit board which has a driver circuit for energizing the liquid crystal display panel, the printed-circuit board having a second group of leads. An electrically conductive resilient spacer is disposed between the liquid crystal display panel and the printed-circuit board. The first and second groups of leads are electrically connected to each other by the electrically conductive spacer. The edge of the liquid crystal display panel is resiliently pressed against the holder bezel by the electrically conductive resilient spacer. A display panel support positioned in the frame and mounted on the printed-circuit board has a base integrally joined to the frame and a resilient wing extending from the base. The liquid crystal display panel is resiliently pressed against the holder bezel remotely from the first group of leads by the resilient wing.

Liquid crystal display panel assembly with resilient display panel

A clamp structure clamps superimposed circuit boards to a support plate portion of a rangefinder case in a still camera. The clamp structure includes first and second support arms spaced in confronting relation from each other by a distance greater than the thicknesses of the superimposed circuit boards and the support plate portion. The first and second support arms are disposed in sandwiching relation to the circuit boards and the support plate portion. A rod is inserted in a space defined between the second support arm and the lowermost circuit board which faces the second support arm while the first support arm is being held against the uppermost circuit board which faces the first support arm. With the rod inserted in the space, the circuit boards are fastened to the support plate portion between the first and second support arms under the resiliency of either an elastic member which is placed between the first support arm and the uppermost circuit board or the resiliency of the first and second support arms themselves.

Clamp structure for plural members

An image processing apparatus applicable to a multi-media copying machine with which multiple different recording media are usable includes a scanner for reading a document image and converting it into an electrical image signal, a floppy disk drive, an MPU and other controllers, and a printer for printing out an image on paper. The apparatus has not only a document-to-paper copying function but also a document-to-disk copying function and a disk-to-paper copying function.

Growing community of inventors

Tokyo, Japan

Masaki Sano