Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Masaki Okuno

Yasuhisa Sato

Hajime Yamamoto

Rinji Sugino

Shigeo Satoh

Sadahiro Kishii

Masanori Terahara

Hiroshi Morioka

Toshiro Nakanishi

Kaina Suzuki

A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.

Semiconductor device manufacturing method

A semiconductor device includes a gate electrode formed over a semiconductor substrate, and a sidewall spacer formed on a sidewall of the gate electrode. The sidewall spacer formed along the sidewall parallel to a gate length direction of the gate electrode has a first thickness, and the sidewall spacer formed along the sidewall parallel to a gate width direction of the gate electrode has a second thickness that is greater than the first thickness.

Semiconductor device and manufacturing method of the same

A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.

A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

Semiconductor device and method for manufacturing the same

A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of the fin and having side walls in conformity with the side walls of the fin; source/drain regions formed in the fin on both sides of the gate electrode; side wall insulating films including a first portion formed on the side walls of the conductive gate electrode and a second portion formed on the side walls of the fin and having an opening in the source/drain regions extending from an upper edge to a lower edge of each of the side walls; a silicide layer formed on each surface of the source/drain regions exposed in the opening of the second side wall insulating film; and source/drain electrodes contacting the silicide layers.

Fin-type semiconductor device with low contact resistance and its manufacture method

Fin-type semiconductor device with low contact resistance

A dry cleaning method for removing metal contaminants from a surface of an oxide film such that no substantial etching of the oxide film occurs, includes the steps of supplying a halide gas containing an element that is selected from the group IIIa elements, group IVa elements and the group Va elements in a form of halide, to the oxide film, thereby dry cleaning the surface of the oxide film.

Dry cleaning process for cleaning a surface

A method of forming a silicon oxide film by setting a silicon wafer in a chamber capable of introducing oxidizing gas and being evacuated and by heating the silicon wafer in an oxidizing atmosphere. The method includes the steps of: transporting the silicon wafer into the chamber without contacting the silicon wafer with air; introducing an ozone containing gas into the chamber and setting the interior of the chamber to a predetermined pressure; and heating the silicon wafer to a predetermined temperature and oxidizing the surface of the silicon wafer. The predetermined pressure is preferably between 200 Torr and 0.1 Torr. Ozone may be generated from oxygen by applying ultraviolet rays to the upper space of a silicon wafer. The temperature of ozone to be introduced is preferably low. It is preferable to incorporate infrared heating in order not to excessively heat ozone and to heat a silicon wafer to a high temperature.

Method of forming thin silicon oxide film with high dielectric breakdown

A dry cleaning process for removing metal contaminants from a surface of an oxide film includes the steps of: forming a reaction area on the oxide film such that a silicon surface is formed in correspondence to the reaction area, supplying a dry cleaning gas selected from a group essentially consisting of chlorine, bromine, hydrogen chloride, hydrogen bromide and a mixture thereof, to the oxide film including the reaction area, to produce silicon halide molecules as a result of a reaction between the dry cleaning gas and the silicon surface, supplying the silicon halide molecules to a surface of the oxide film, and removing metal elements existing on the surface of the oxide film as a result of a reaction between the metal element and the dry cleaning gas under a presence of the silicon halide molecules.

Growing community of inventors

Kawasaki, Japan

Masaki Okuno