Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Vlsi Limited

Fujitsu Microelectronics Limited

Masaki Okada

Tomohiro Fukuoka

Kazuhiko Okada

Hiromi Yokoi

Nobuyuki Hattori

An arbitration device and method including validating a second signal after a first signal is selected for a given number of times when the first signal and the second signal conflict, where the first signal has a first priority based on a priority order corresponding to a plurality of processes and the second signal has a second priority lower than the first priority.

Arbitration device, arbitration method, and electronic apparatus

A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

Data transfer control device and data transfer control method

The present invention relates to an image recorder including a selector circuit. Image data output from the image recorder, or output data of an encoder, is format converted in a format conversion circuit, and provided to a selector circuit arranged in a stage either preceding or following a pre-process circuit. The selector circuit selects one of input data from a CCD and input data from the format conversion circuit and provides the selected input data to the pre-process circuit. The output data of the encoder is then fed back. This configures a pseudo imaging system.

Image recorder

An image data encoding apparatus performs a two-step process to expand and compress digital image data. The apparatus includes a transform unit for performing orthogonal transform of the image data in a block-by-block manner and generating transform coefficient data. In the first step of the encoding step, a quantizer quantizes the transform coefficient data using a first quantization coefficient to generate first code data. A coefficient operation unit receives the first code data and computes a second quantization coefficient for determining an optimal compression rate of the image data. In the second step of the encoding process, the quantizer receives the second quantization coefficient and quantizes the transform coefficient data to generate second code data. The transform coefficient data is stored in a memory. By optimally compressing the image data, a high image data compression rate is achieved, which allows a greater number of compressed images to be stored. Also, by pipelining the encoding and decoding processes, image processing time is decreased.

Image data encoding apparatus

Disclosed is a circuit which receives a supply voltage from a power supply and generates a voltage of a desired level different from that of the supply voltage. The circuit includes an oscillation circuit, a supply voltage generator, a first interconnection and a control circuit. The oscillation circuit generates an oscillation output signal. The supply voltage generator is responsive to the oscillation output signal from the oscillation circuit and generates a voltage of a predetermined level. The first interconnection connects the supply voltage generator to an internal circuit which is to be supplied with the voltage generated by the supply voltage generator. The internal circuit is also connected via a second interconnection to a power supply. The control circuit is provided between the first interconnection and the second interconnection as a variable resistor circuit which is responsive to the oscillation output signal from the oscillation circuit. The control circuit changes its resistance in synchronism with the end of the generation of the voltage of the predetermined level by the supply voltage generator.

Supply voltage generator

An integrated circuit includes a circuit chip, one or more circuits provided on the circuit chip, an input/output circuit provided on the circuit chip in electrical connection to the one or more circuits for transmitting and/or receiving an information signal to and from an external circuit outside the circuit chip, a plurality of resistance areas provided on the circuit chip for electrical connnection therewith for providing a predetermined input and/or output impedance of the integrated circuit, and a plurality of connection pads provided on the circuit chip in correspondence to the plurality of resistance areas for electrical connection therewith, for electrical connection to the external circuit. The plurality of resistance areas include a plurality of elongated resistance strips connected in series and extending parallel with each other, wherein each elongated resistance strip in each resistance area extends on the major surface of the circuit chip in a predetermined direction.

Growing community of inventors

Kasugai, Japan

Masaki Okada