Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Masaki Ogihara

Syuso Fujii

Shizuo Sawada

Kenji Numata

Satoru Takase

Kiyofumi Sakurai

Yasuhiko Mizuno

Rei Itsuki

Yoshio Okada

Ryo Imura

In an emigration control method, information on a passport-issue-allowed person and image data for specifying the person are stored in a storage. Image data for specifying a person who owns the passport to be inspected by an emigration inspection and information for specifying the passport-issue-allowed person are received. The passport-holding-person specifying image data is stored into an emigrant information storage in correspondence with the passport-issue-allowed person specifying information The passport-issue-allowed person specifying image data, the passport-issue-allowed person information, and the passport-holding-person specifying image data are extracted based upon the received passport-issue-allowed person specifying information.

Emigrant reception system, emigrant gate system, emigrant control system, emigrant control method, passport applicant information management method, layout of emigrant gate, immigrant reception system, immigrant gate system, immigrant control system, immigrant control method, layout of immigrant gate system, and passport

In one embodiment, a product distribution management system includes a product management center. The product management center includes a management device to receive product security data on a product from a distribution site and a product management database to store the data received from the distribution site for use in a product authentication process. The data includes product identification information and security information used to authenticate the product.

Distribution management method and system

In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

Dynamic type memory

A semiconductor integrated circuit device is described. The semiconductor device includes a switching signal generator having an output terminal which outputs a switching signal to change refresh modes. The semiconductor device also includes a first address buffer having an output terminal which outputs a first address signal, a second address buffer having an output terminal which outputs a second signal, a decoder having a first input terminal which receives the first address signal and having a second input terminal, a sense amplifier controller having an input terminal, and a switch having a first input terminal which receives the switching signal, a second input terminal which receives the second address signal, a first output terminal which outputs the second address signal to the second input terminal of the decoder and a second output terminal which outputs the second address signal to the input terminal of the sense amplifier controller, the switch being controlled by the switching signal.

Semiconductor memory device allowing change of refresh mode and address

A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device includes an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and an active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further includes a receiving for taking in a decision signal for determining the product specification a, switching signal generator, connected to the receiving device, for producing a switching signal for changing the product specification based on the decision signal, and switching device which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.

Semiconductor integrated circuit device allowing change of product

A semiconductor memory device includes a buffer for outputting an address signal and a decoding circuit having an input for receiving the address signal. A switch electrically connects the buffer to the input of the decoding circuit if a refresh mode specifying signal specifies a first data refresh mode, and electrically disconnects the buffer from the input of the decoding circuit if the refresh mode specifying signal specifies a second data refresh mode different from the first data refresh mode. An activating/deactivating circuit activates the input of the decoding circuit if the refresh mode specifying signal specifies the first data refresh mode and deactivates the input of the decoding circuit if the refresh mode specifying signal specifies the second data refresh mode.

A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.

Semiconductor device having different impurity concentration wells

A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.

Dynamic memory

A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device comprises an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further comprises receiving means for taking in a decision signal for determining the product specification, switching signal generator means, connected to the receiving means, for producing a switching signal for changing the product specification based on the decision signal, and switching means which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.

Memory cells including at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS for transferring a potential to the word line. The word line drive circuit is controlled by a output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.

Dram using word line potential circuit control

A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.

A semiconductor integrated circuit capable of changing a product specification comprises a first circuit section having a first function, a second circuit section having a second function, and active signal generator means for producing an active signal for activating either the first circuit section or the second circuit section. To change the product specification, the integrated circuit further comprises means for receiving a decision signal, switching signal generator means, connected to said receiving means, for producing a switching signal for changing the product specification according to the decision signal, and switching means for receiving the active signal and the switching signal and for supplying the active signal to either the first circuit section or the second circuit section according to the switching signal.

Semiconductor integrated circuit allowing change of product

Memory cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.

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Yokohama, Japan

Masaki Ogihara