Hitachi, Ltd.

Masaki Nagao

Hiroyuki Uchiyama

Hiroyuki Miyazawa

Yoshiyuki Kaneko

Kozo Watanabe

Kyoichiro Asayama

Atushi Ogishima

Naokatsu Suwanai

Hiroki Soeda

Kazuya Endo

Takashi Yoneoka

Yutaka Kobayashi

Yoshitaka Tadaki

Masayuki Kojima

Hisashi Nakamura

Kazuo Nojiri

Atsuyoshi Koike

Toshihiro Sekiguchi

Hiromichi Enami

Jun Murata

Osamu Kasahara

Atsushi Ogishima

Hiroko Kaneko

Michimasa Funabashi

Toshio Maeda

Yasuo Kiguchi

Kazuya Kadota

Tadashi Chikahara

Masato Sadaoka

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Semiconductor memory circuit device and method for fabricating a

A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

Semiconductor integrated circuit, method of fabricating the same and

Method of making a semiconductor memory circuit device

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.

Semiconductor memory circuit device and method for fabricating same

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Koganei, Japan

Masaki Nagao