Kabushiki Kaisha Toshiba

Tosbac Computer System Company Limited

Toshiba Micro-Computer Engineering Corp.

Masaki Momodomi

Yoshihisa Iwata

Tomoharu Tanaka

Yasuo Itoh

Riichiro Shirota

Fujio Masuoka

Yoshiyuki Tanaka

Seiichi Aritome

Takashi Mori

Hideko Odaira

Masamichi Asano

Ryouhei Kirisawa

Hideo Kato

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Koji Sakui

Kazunori Ohuchi

Ryozo Nakayama

Tetsuo Endoh

Osamu Ikeda

Shigeyoshi Watanabe

Minori Kajimoto

Masahiko Chiba

Mitsugi Ogura

Shinji Saito

Hiroshi Iwahashi

Takehiro Hasegawa

Hiroshi Nakamura

Satoshi Inoue

Hideki Sumihara

Koichi Toita

Tetsuo Endo

Daisaburo Takashima

Takuya Futatsuyama

Junichi Miyamoto

Fumio Horiguchi

Toshiharu Watanabe

Yoshihisa Sugiura

Takaya Suda

Hidenobu Minagawa

Akira Narita

Shuso Fujii

Kazuto Suzuki

Takaki Kumanomido

Tetsuro Endoh

A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.

Semiconductor device, electronic card and pad rearrangement substrate

A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

Memory system having improved random write performance

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Non-volatile semiconductor memory device and memory system using the same

A pad rearrangement substrate includes an internal terminal provided on a mounting plane of a dielectric substrate, an external terminal provided on the external terminal plane of the dielectric substrate, an internal wiring pattern connecting the external terminal to the internal terminal, an antenna pattern provided at a corner portion of the external terminal plane of the dielectric substrate, an external terminal provided on the external terminal plane of the dielectric substrate, and a dielectric layer. The antenna pattern is connected to the dummy external terminal. The dielectric layer coats the external terminal plane of the dielectric substrate except the external terminal and the dummy external terminal.

Pad rearrangement substrate

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Non-volatile semiconductor memory device with an improved verify voltage generator

In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.

NAND-type EEPROM having bit lines and source lines commonly coupled

A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

Electrically erasable programmable read-only memory with threshold value

An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

Non-volatile semiconductor memory device with nand type memory cell

A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

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Yokohama, Japan

Masaki Momodomi