Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Other

Ubishi Denki Kabushiki Kaisha

Masaki Kumanoya

Katsumi Dosaka

Yasuhiro Konishi

Hideshi Miyatake

Hideto Hidaka

Akira Yamazaki

Kazuyasu Fujishima

Hisashi Iwamoto

Takahiro Komatsu

Kouji Hayano

Hideaki Abe

Yasuhiro Ishizuka

Katsumitsu Himukashi

Tsukasa Saiki

Yoshinori Inoue

Hiroyuki Yamasaki

Tsutomu Yoshihara

Yuto Ikeda

Youichi Tobita

Kazuhiro Tsukamoto

Masaki Shimoda

Toshiyuki Omoto

Yasumasa Nishimura

Hirofumi Shinohara

Yukihiko Shimazu

Toru Shimizu

Yoichi Tobita

Katsunori Sawai

Tsukasa Saika

Konishi Yasuhiro

A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

Synchronous semiconductor memory including register for storing data input and output mode information

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Semiconductor memory device

A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer , while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

Semiconductor memory device with an internal voltage generating circuit

A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM

A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

Semiconductor memory device including dynamic type memory and static

A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.

Microcomputer

In an operation of transferring data between a DRAM array and an SRAM array through a bidirectional transfer gate circuit, data blocks on a selected one in the DRAM array are sequentially selected in a high speed mode, word lines are sequentially selected in the SRAM array, so that data is transferred in a time division multiplexing manner between the DRAM array and the SRAM array in units of data block. A cache block size in a semiconductor memory device containing a cache can be externally changed depending on the application with the internal configuration maintained unchangedly.

Semiconductor memory capable of transferring data at a high speed

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Hyogo, Japan

Masaki Kumanoya