Hitachi, Ltd.

Hitachi Information Technology Co., Ltd.

Masaki Kouno

Masato Hamamoto

Kazutaka Mori

Keiichi Higeta

Mitsugu Kusunoki

Atsushi Wakahara

Kazumi Hatayama

Yoshikazu Kiyoshige

Michinobu Nakao

Hideyuki Takahashi

Tomoji Nakamura

Hidefumi Yoshida

Koichiro Natsume

A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising meansto generate identical pattern sequences repeatedly and meansto control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.

Test method of semiconductor intergrated circuit and test pattern generator

A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

Manufacturing method of semiconductor device

Growing community of inventors

Ome, Japan

Masaki Kouno