Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Toshiba Digital Solutions Corporation

Masaki Kondo

Takashi Izumida

Nobutoshi Aoki

Tsukasa Nakai

Hikari Tajima

Fumitaka Arai

Nobuaki Yasutake

Takahisa Kanemura

Hiroki Tokuhira

Toshiyuki Enda

Hideaki Aochi

Ryota Katsumata

Daisuke Hagishima

Hiroyoshi Tanimoto

Takayuki Okamura

Masaru Kito

Takuya Futatsuyama

Takashi Kobayashi

Kei Sakamoto

Keiji Hosotani

Eietsu Takahashi

Yoichi Minemura

Toshiaki Edahiro

Takeshi Sonehara

Kiyohito Nishihara

Norihiro Fujita

Tadayoshi Uechi

Tohru Maruyama

Sanae Ito

Takashi Kurusu

Tomomi Kusaka

Hiroshi Maejima

Riichiro Shirota

Masaru Kidoh

Atsushi Fukumoto

Ryo Fukuda

Akihiro Nitayama

Makoto Mizukami

Tadashi Iguchi

Hidehiro Shiga

Tomoya Sanuki

Tatsuya Kato

Makoto Fujiwara

Fumiki Aiso

Yohji Watanabe

Masao Shingu

Hiroshi Akahori

Masaaki Higuchi

Shigeo Kondo

Yusuke Higashi

Daigo Ichinose

Hirokazu Ishida

Takashi Ichikawa

Jyunichi Ozeki

Hidenobu Nagashima

Tetsu Morooka

Mitsutoshi Nakamura

Naoki Kusunoki

Kazuaki Iwasawa

Nobuyuki Momo

Hideto Horii

Takashi Shigeoka

Masakazu Goto

Takeshi Murata

Muneyuki Tsuda

Yingkang Zhang

Tomomi Yoda

According to one embodiment, a semiconductor memory device includes first and second semiconductor layers and a first conductive layer. The first and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked above the first semiconductor layer in a second direction intersecting the first direction. The first conductive layer intersects the first and second semiconductor layers and extends in the second direction. The first conductive layer includes first and second portions intersecting the first and second semiconductor layers respectively. A width of the first portion in the first direction is smaller than a width of the second portion in the first direction. A thickness of the first semiconductor layer in the second direction is larger than a thickness of the second semiconductor layer in the second direction.

Semiconductor memory device

A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.

Semiconductor memory device including memory cells at opposing sides of semiconductor

A semiconductor memory device includes first conductive layers stacked and second conductive layers stacked in a first direction. The second conductive layers spaced from the first conductive layers in a second direction intersecting the first direction. A first memory pillar is between the first conductive layers and the second conductive layers in the second direction. The first memory pillar extends in the first direction and has a first length in the second direction. A second memory pillar is between the first conductive layers and the second conductive layers in the second direction. The second memory pillar is adjacent to the first memory pillar. The second memory pillar extends in the first direction and has a second length greater than the first length in the second direction.

An example semiconductor device includes: n conductive layers including first to nconductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nconductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to ncharge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

System and method for controlling semiconductor memory device including multiple charge storage regions

According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.

Non-volatile semiconductor memory device

A data processing device according to an embodiment includes a sub-vector group generating unit, a codebook generating unit, and a converting unit. The sub-vector group generating unit generates, from a feature vector set of N number of D-dimensional feature vectors, M number of sub-vector groups (where M&#x3c;D holds true). Each of the M number of sub-vector groups includes N number of dimension-variable sub-vectors obtained from the N number of D-dimensional feature vectors. For each of the M number of sub-vector groups, the codebook generating unit performs clustering of the N number of dimension-variable sub-vectors, and generates a codebook in which the representative vector of each cluster is associated with an index. The converting unit performs product quantization using the codebook and converts each of the N number of D-dimensional feature vectors into a compressed code made of a combination of M number of indexes.

Data processing device, data processing method, and computer program product

According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

Semiconductor memory device applying different voltages to respective select gate lines

A semiconductor memory device includes a semiconductor substrate, a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate, a plurality of first memory cells arranged on a first side surface of the pillar along the first direction, and a plurality of second memory cells arranged on a second side surface of the pillar along the first direction. The memory device further includes a plurality of first control gate layers respectively connected to the first memory cells, a plurality of second control gate layers respectively connected to the second memory cells, and a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer.

A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Semiconductor memory device with charge-diffusion-less transistors

A non-volatile memory device includes a conductive layer, a first electrode layer provided side by side with the conductive layer in a first direction, a second electrode layer provided between the conductive layer and the first electrode. At least a part of the second electrode on the conductive layer side has a work function smaller than a work function of the first electrode. The device further includes a first channel body extending through the first electrode layer in the first direction and a charge storage portion provided between the first electrode layer and the first channel body.

Non-volatile memory device

According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.

Semiconductor device

According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.

A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent to the second electrode layer, a fourth electrode layer adjacent to the third electrode layer, and a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in a first direction. The device further includes a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body. The circuit providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, the fourth electrode layer with a third potential between the first potential and the second potential and the channel body with a potential rising in the first direction.

Non-volatile memory device and method for reading out data

According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.

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Kawasaki, Japan

Masaki Kondo