Fujitsu Corporation

Masaki Kira

Hiroya Kawasaki

Shiro Uriu

Noriko Samejima

Takashi Tabu

Kenichi Okabe

Naoyuki Izawa

Shigeru Sekine

Atsushi Fujihira

Kazumasa Sonoda

Yoshio Morita

Hidetoshi Iwasa

Hisato Kawano

Kiyofumi Mitsuze

Yukinaga Toyoda

A switching system for controlling internal apparatuses provided within an exchange system includes a central controller and a switching module including a plurality of objective apparatuses, each objective apparatus including a control data end unit, controlled by the central controller based on DMA communication and SD/SCN signal. Further, the central controller includes a first processor access controller which transfers control data to the control data end unit, in order to check and control each of objective apparatus, based on the DMA communication and the SD/SCN signal. The switching module includes a second processor access controller which relays the control data transferred between the first processor access controller and a plurality of control data end units-based on the DMA communication and the SD/SCN signal. According to the present invention, it is possible to realize high speed data transfer and high reliability based on the DMA communication and the SD/SCN signal between the central controller and each objective apparatus.

Switching system for controlling internal apparatuses in an exchange system

A start/stop setting section is provided on the upstream side of a dual-configuration ATM switch, and a start/stop detection section is provided on the downstream side for each of a working and a protection line. At the initiation of quality monitoring, the start/stop setting section sets a start bit in an incoming cell having a specified identifier, and thereupon starts counting the number of cells whose identifier matches the specified identifier. The start/stop detection section, upon detecting the cell having the start bit, starts counting the number of cells whose identifier matches the identifier of the detected cell. At the end of the quality monitoring, the start/stop setting section sets a stop bit in an incoming cell having the specified identifier, and thereupon stops the counting of cells.

Communication path quality monitoring method and quality monitoring apparatus

A peripheral device cable, connected to a peripheral device, integrally incorporates a subscriber link that is a physical line for transmitting subscriber information in synchronization with a highway clock and a control link that is a physical line for transmitting control data in synchronization with the highway clock. A control data converter controls interfacing between the control data transferred over the control link synchronously with the highway clock and control data that a control unit transmits/receives asynchronously with the highway clock. The subscriber link is connected to a switch.

In-station control system and method

A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device. The simplex unit executes predetermined control upon accepting control data from the apparent acting device.

Apparatus for preventing malfunction at time of duplex unit failure

In the present invention, input data are extracted by a clock and compared with the previous input data. A cyclic counter is provided for cyclically counting clock signals in each noise erasure time period (the maximum retaining time of a signal referred to as noise). When a change is detected in input data, the counter value is stored. When the input data indicate no changes, the counter value and the stored counter value are compared. If a non-coincident result is outputted, it indicates that the noise erasure time has not passed since the input data indicated a change. Therefore, the input data are not outputted. If a coincident result is outputted, it indicates that the cyclic counter counted one cycle. That is, the noise erasure time has passed. Therefore, the input data are outputted since the input data are not recognized as noise.

Circuit for providing digital data having high clarity in a digital

A time-multiplexed highway line designating system used in a time divisional electronic switching unit comprises line interface units each being provided corresponding to each line, a storing unit provided in the interface unit for storing time slot information specific to each line processed in a time divisional manner, and a timing generating circuit provided in the interface unit for generating from the time slot information a timing for the line.

Growing community of inventors

Kawasaki, Japan

Masaki Kira