Kabushiki Kaisha Toshiba

Toshiba Tec Kabushiki Kaisha

Masaki Ichikawa

Akira Umezawa

Kazushige Kanda

Takehiro Hasegawa

Tsuneaki Fuse

Takuya Fujimoto

An image forming apparatus includes a plurality of print heads, a sensor, a processor, and an image forming unit. The plurality of print heads are arranged in parallel. The sensor detects a color shift amount of each color to be printed by the plurality of print heads in a main scanning direction based on an output result of a test pattern by the plurality of print heads. The processor sets a color shift correction value for correcting the color shift amount on the basis of a color having a largest color shift amount. The processor controls light emission of the plurality of print heads based on the color shift correction value and image data. The image forming unit forms an image based on the image data on a sheet by light emission of the plurality of print heads.

Image forming apparatus having light emission control and image forming method

An image forming apparatus includes a printer, a sensor, and a processor. The printer forms an image with image forming material of colors on a medium. The sensor detects the image forming material of each color on the medium. The processor forms a pattern with the image forming material of the colors on the medium using the printer, acquires a position of a pattern of each color using the sensor, and after executing correction for bringing positions where images of the other colors are formed close to a position where an image of a reference color is formed based on the position of each pattern, corrects a position where either an image of a first color or an image of a second color is formed by the printer based on a distance between patterns of the first color and second color furthest away from each other.

Image forming apparatus, computer-readable storage medium, and image forming method with position acquisition and correction

An image forming apparatus includes a laser device, a sensor, and a control unit. The laser device emits laser light which is reference for image forming. The sensor detects the laser light emitted from the laser device. The control unit changes an output direction of the laser light emitted from the laser device if the laser light is not detected by the sensor.

Image forming apparatus and laser light detecting method

A reference current generating circuit includes first and second standard current generating circuits to generate first and second standard currents, respectively and first and second trimming circuits to generate first and second reference circuits by trimming the standard current values outputted from the standard current generating circuits. The second standard current generating circuit operates for a part of an operation period of the first standard current generating circuit. The value of the first reference current is compared with a value of the second reference current, and controlled so as to approach the value of the second reference current by a trimming controller.

Reference current generating circuit

A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.

Semiconductor device for generating power on reset signal

A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Growing community of inventors

Shizuoka, Japan

Masaki Ichikawa