Fujitsu Corporation

Masaki Hirota

Kazuto Nishimura

Hiroshi Tomonaga

Haruo Yamashita

Michio Kusayanagi

Tomohiro Shinomiya

Akihiro Hata

Nagao Shimada

Kou Takatori

Shigeyuki Kobayashi

Yasushi Sasakawa

A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state.

Packet relaying apparatus and packet relaying method

A packet processing device includes a memory, and circuitry coupled the memory and configured to perform: sampling received packets at a predetermined interval, detecting a plurality of bursts in which received packets are continuously detected by the sampling, calculating, for each of the plurality of bursts detected, a front edge period based on the received packet detected first among the bursts, calculating, for each of the plurality of bursts detected, a rear edge period based on the received packet detected last among the bursts, deciding the longer period between the front edge period and the rear edge period as a burst period, and controlling transfer of the received packets based on the decided burst period.

Packet processing device and packet processing method

A packet relay device includes: a first buffer configured to store a packet; and a processor coupled to the first buffer and configured to: calculate a delay time for reading from the first buffer based on a packet length and a packet interval of the packet which is inputted to the first buffer, and delay the packet according to the calculated delay time, the packet being read from the first buffer.

Packet relay device and packet transmission device

A communication device includes: first and second memories configured to store first and second packets in first and second queues, respectively; a processor configured to: select a packet to be transmitted by selecting the first packet in priority to the second packet, read the selected packet from the first or second queue, and detect the first packet stored in the first queue during reading of the second packet from the second queue; and a third memory configured to hold copied data relating to the second packet, wherein when detecting the first packet, the processor is configured to cause an internal or external part of the communication device to discard the currently read second packet, read the first packet stored in the first queue, and read the copied data from the third memory after completion of the reading of the first packet.

Communication device, method and system for queueing packets to be transmitted

A communication device includes a memory to store data and a processor to receive data, to convert the received data and a same data of the received data among the stored data into a predetermined format, and to transmit data resulting from the data conversion.

Communication device and communication method

A relaying apparatus includes a memory that stores a program including a procedure, and a processor that executes the program including the procedure, wherein the procedure includes delaying, when received packet data includes a synchronization message for any one of a frequency synchronization and a time synchronization, a transmission of the received packet data so that a period of time for a relaying process attains a given value.

Relaying apparatus and relaying method

A data block output apparatus includes a first queue that stores data blocks of first traffic; a second queue that stores data blocks of second traffic and is read preferentially over the first queue; a monitoring unit that monitors for occurrence of data blocks read out of the second queue after reading of a data block from the first queue is completed; and a control unit that controls a data block interval between completion of reading of one data block in the first traffic and a start of reading of a next data block in the first traffic when occurrence frequency of the data blocks read out of the second queue after the reading of one data block from the first queue is completed is equal to or higher than a predetermined value.

Data block output apparatus, communication system, data block output method, and communication method

A method for preventing a control packet loop in a network realizing node redundancy or circuit redundancy based on a rapid spanning tree protocol or a multiple spanning tree protocol is disclosed. The method includes the steps of: detecting a loop of a control packet of the rapid spanning tree protocol or the multiple spanning tree protocol; and discarding the control packet by which the loop is detected so as to prevent occurrence of the loop of the control packet.

Method for preventing control packet looping and bridge apparatus using the method

Disclosed is a method of setting a bidirectional path between a first node and a second node in a network. A first path from the first node to the second node is established by a first path establishing procedure in which a first path message including a record of a route through which the first path message is forwarded from the first node to the second node. A second path from the second node to the first node along the route of the first path in the backward direction is established by a second path establishing procedure in which a second path message including a route specification determined based on the record of the route included in the first path message is transferred from the second node to the first node.

Method of setting bidirectional path, and communication system and node device for providing the same

In a data transmission device and method provided with duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches is faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.

Data transmission device

In a layer 2 communication device included in multiple layer 2 networks, an identifying unit identifies a layer 3 control packet from among packets passing through, and an embedding unit embeds routing control information for the layer 2 network in the layer 3 control packet. In a layer 3 communication device connected to the multiple layer 2 networks, a selecting unit selects from the multiple layer 2 networks, an optimum L2 network, that is a layer 2 network forming an optimum communication route, based on a communication destination, and a setting unit sets a packet to be transmitted to the optimum L2 network.

Network system, layer 3 communication device, layer 2 communication device, and route selection method

A method for time-division multiplexing including steps of generating a plurality of first signals and a plurality of second signals to which specific pulse trains for frame synchronization are allocated respectively; generating low speed signals of plural channels including the first and second signals and transmission signals; a conversion step; and time-division multiplexing the low speed signals after the conversion step, thereby obtaining high speed signals. When applied to SDH, for example, the first and second signals may be A1 bytes and A2 bytes respectively, and the transmission signals may ho payload signals. According to one aspect of the invention, at the conversion step, the first and second signals in each channel are panty convened into either of '1/0' alternating signals and '0/1' alternating signals. Consequently, it becomes possible to reduce the number of successive same code and to diminish the deviation of the mark rate.

Method for time-division multiplexing

A burst synchronizing circuit synchronizes a received data signal in a burst fashion and sampling phases with which the received data signal is sampled. A first part samples a data pattern with different sampling phases. A second part selects the received data signal sampled with an optimal sampling phase based on sampling phases with which the data pattern is detected.

Growing community of inventors

Kawasaki, Japan

Masaki Hirota