Fujitsu Corporation

Olympus Corporation

Fujitsu Semiconductor Limited

Masaki Arai

Kanae Nakagawa

Yasumoto Tomita

Koichi Takahashi

Shinichi Sutou

Masatoshi Haraguchi

Mitsuharu Wakayoshi

Takashi Hanai

Kuninori Ishii

Masanori Yamanaka

Kotaro Taki

A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

Barrier synchronization circuit, barrier synchronization method, and parallel information processing apparatus

A program rewrite method executed by a computer, the method includes rewriting a program to output a first output group by performing operations for a first variable among a plurality of variables with a plurality of data types; rewriting the program to output a second output group by performing operations for a second variable among the plurality of variables with a plurality of data types; identifying, from the first output group and the second output group, a third output group that satisfied a predetermined criterion as a result of executing the rewritten programs; determining a data type that corresponds to the third output group as a use data type; and outputting a program in which the use data type is set for each of the plurality of variables.

Program rewrite device, storage medium, and program rewrite method

A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.

Barrier synchronization system and parallel information processing apparatus

An information processing apparatus, a non-transitory computer-readable storage medium for storing an information processing program, and an information processing method are described. In an embodiment, provided is a solution to efficiently determine a degree to which each of a plurality of simplification processes is applied to a program. For example, an information processing apparatus includes: a storage device that stores program instructions; and a processor that executes the program instructions including selecting a first candidate value from among a plurality of candidate values included in a first set, based on an evaluation result for a plurality of execution results generated at a first position, and selecting a second candidate value from among the plurality of candidate values included in a second set, based on an evaluation result for the plurality of execution results generated at a second position.

Information processing apparatus, non-transitory computer-readable storage medium for storing information processing program, and information processing method

An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: receive input of an input program in which a plurality of statements is written in a loop; generate a counting program for causing a computing machinery to execute a process of counting the number of cache misses and the number of cache hits that are expected when the loop is executed for each of pairs of the statements by rewriting the input program; and split the loop into a plurality of loops based on the number of cache misses and the number of cache hits counted in the process.

Information processing apparatus and information processing method

An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address in the first memory, at which an instruction included in a target program is stored. The processor is configured to simulate access to a second memory, such as a cache memory, corresponding to an access request for access to the first address on a basis of configuration information of the second memory. The processor is configured to generate first information, such as cache profile information, indicating whether the access to the second memory regarding the instruction is a hit or miss. The processor may be configured to acquire a number of cache misses for each of a plurality of pieces of arrangement information, and select a piece of arrangement information where the number of cache misses is smallest. Where the second memory is divided into a plurality of cache sets, the processor may generate the first information for each of the respective cache sets in parallel with each other. A cache set number of the second memory may also be identified.

Information processing apparatus and method including simulating access to cache memory and generating profile information

A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.

Storage medium storing cache miss estimation program, cache miss estimation method, and information processing apparatus

A storage unit stores source code including loop processing that is written with an array referenced by an index, a loop variable, and a parameter. A computing unit generates a conditional expression indicating that the index of the array satisfies a predetermined condition, using the loop variable and the parameter. The computing unit generates determination information on the parameter, by eliminating the loop variable from the conditional expression through formula manipulation. Then, the computing unit generates object code corresponding to the source code in accordance with the determination information.

Information processing apparatus and compilation method

In the present invention, a management apparatus includes a unit configured to store management information including a throughput of each of a plurality of computers, a unit configured to acquire a request value which includes a throughput that is required for executing a program from a program execution computer to which execution of a program has been assigned among a plurality of computers, a selecting unit configured to select a computer of a throughput compliant with the request value from among a plurality of computers, and a switchover control unit configured to allocate the program allocated to the program execution computer to the selected computer.

Process allocation management apparatus, system and method

A procedure, which is performed by a processor of a variable updating device, includes: (a) judging whether or not the cache set is a cache set selected in advance; (b) in a case in which the corresponding cache set is judged to be the cache set selected in advance, judging which of (1) a hit and (2) a miss has occurred; and (c) carrying out a first processing that, in a case in which it is judged that the miss has occurred, updates a miss variable that expresses a number of times that misses have occurred and stores the address information in the storage portion, and a second processing that, in a case in which it is judged that the hit has occurred, updates a hit variable that expresses a number of times that hits have occurred.

Variable updating device and variable updating method

A loop distribution group detection program for causing a computer to execute a process including, converting a loop distribution target program into a test program having a cache miss measurement instruction, by dividing a loop in the loop distribution target program into plural distribution loops based on a loop distribution specification parameter, sequentially executing the test program while varying the loop distribution specification parameter, extracting loop distribution candidates, for which the number of cache misses exceeds a reference value, as a first loop distribution candidate group, and extracting loop distribution candidates with not exceeding the reference value, as a second loop distribution candidate group, and excluding loop distributions from execution target candidates for the test program, by comparing a loop distribution based on the loop distribution specification parameter with loop distributions of the loop distribution candidates in the first loop distribution candidate group.

Loop distribution detection program and loop distribution detection method

A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.

Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array

In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Software development tool program

A reflective surface for detection is provided in an object being detected. Laser light condensed by a condensing lens is emitted from a laser light source and angle detection is performed by performing angle detection of the reflected light. The reflected light is irradiated onto a beam splitter and the optical path thereof is split by an optical path splitting surface to form luminous flux spots on light receiving surfaces of two four section light receivers. Optical path lengths from the reflective surface for detection to the respective light receiving surfaces are changed enabling the angle detection sensitivity to be altered. In an angle detection apparatus, an optical signal switch system, and an information recording and reproduction system, it is possible to make multiple detections of an inclination angle of a detection object using a compact structure. Consequently, improvements in various performances such as apparatus reliability, inclination angle detection precision, and detection range can be achieved.

Growing community of inventors

Kawasaki, Japan

Masaki Arai