Fujitsu Corporation

Masaki Aoki

Takashi Eshita

Hirotaka Tamura

Kenichi Yamamoto

Ko Nakamura

Keizo Morita

Hideki Takauchi

Yoshihiro Sato

Akio Itoh

Koji Takahara

Norihisa Murayama

Yuji Sato

Masahito Morishima

Mitsuteru Mushiga

A semiconductor memory device includes a memory cell, a reference cell, a first current source configured to cause a first current to flow through the memory cell, a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell, a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell, and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is equal to a midpoint between the voltage drop across the memory cell having a data value of '0' stored therein and the voltage drop across the memory cell having a data value of '1' stored therein.

Semiconductor memory device and method of controlling semiconductor memory device

A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side.

Semiconductor storage device

A magnetic memory device including a multivalued magnetic memory cell whose electric resistances become first to fourth resistance value when first to fourth information are respectively stored, a first reference cell larger than the first resistance value and smaller than the second resistance value, a second reference cell larger than the second resistance value and smaller than the third resistance value, a third reference cell larger than the third resistance value and smaller than the fourth resistance value, and a read circuit including first to third comparators comparing a signal corresponding to the resistance of the magnetic memory cell and respective signals corresponding to the resistances of the first to third reference cells.

Magnetic memory device and reading method of magnetic memory device

A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.

Semiconductor memory and system

A method of writing into a semiconductor memory device, which includes a resistance memory elementwhich memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage; a transistorincluding a drain terminal connected to one terminal of the resistance memory elementand a source terminal connected to a reference voltage; and a transistorincluding a source terminal connected to the other terminal of the resistance memory element. When a write voltage is applied to the resistance memory elementvia the transistorto switch the resistance memory elementfrom the low resistance state to the high resistance state, a voltage to be applied to the resistance memory elementis controlled at a value which is not less than a reset voltage of the resistance memory elementand less than a set voltage of the resistance memory elementby controlling a voltage to be applied to a gate terminal of the transistorso as to be set at a value which is not less than a total of the reset voltage and a threshold voltage of the transistorand is less than a total of the set voltage and the threshold voltage of the transistor

Semiconductor memory device and method of writing into the same

A semiconductor storage device includes a semiconductor substrate, a source region, a source line, and a bit line. The source region is formed in an element region formed on the semiconductor substrate. The source line is formed to overlap with the source region in planar view. The bit line is formed on a layer higher than the source line.

Semiconductor storage device using magnetoresistive effect element and method of manufacturing the same

An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region.

Resistive memory and data write-in method

In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage.

Semiconductor memory device and method of writing into semiconductor memory device

A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ, MTJand a select transistor connected to the connection node of the magnetoresistance effect elements MTJ, MTJ, a first signal line extended in a first direction and connected to the magnetoresistance effect element MTJ, a second signal line extended in the first direction and connected to the magnetoresistance effect element MTJ, and a third signal line extended in a second direction and crossing the first signal line in a region where the magnetoresistance effect element MTJis formed and crossing the second signal line in a region where the magnetoresistance effect element MTJis formed. When memory information is written into the memory cell, the memory information to be memorized is switched by directions of write currents to be flowed to the first and the second signal lines.

Magnetic memory device and method of writing into the same

A magnetic memory device includes a first signal line (BL) and a second signal line (/BL) extended column-wise; a third signal line (WL) extended row-wise; a memory cell including a first parallelly connected set which is disposed at the intersection of the first signal line and the third signal line, including a first magnetoresistive effect element (MTJ) and a first select transistor (Tr) and having one end connected to the first signal line; a second parallelly connected set which is disposed at the intersection of the second signal line and the third signal line, including a second magnetoresistive effect element (MTJ) and a second select transistor (Tr) and having one end connected to the second signal line; and a read circuit connected to the first signal line and the second signal line, for reading information memorized in the memory cell, based on voltages of the first signal line and the second signal line.

Magnetic memory device, method for writing into magnetic memory device and method for reading magnetic memory device

The magnetic memory device comprises: a memory cell including two magnetoresistive effect elements serially connected to each other, and a select transistor connected to a connection node between the two magnetic resistant devices, a bit line connected to the connection node of the magnetoresistive effect elements via the select transistor, and a read circuit for reading information memorized in the magnetoresistive effect elements, based on a voltage of the connection node outputted to the bit line.

Magnetic memory device, method for writing magnetic memory device and method for reading magnetic memory device

A magnetic memory device comprises a plurality of bit lines BL; memory cells MC disposed at the respective plurality of bit lines, and each including a magnetoresistive effect element MTJ whose resistance value is changed with changes of magnetization direction, and a select transistor Tr connected to the magnetoresistive effect element MTJ, the magnetoresistive effect element MC having one terminal connected to the bit line BL and the other terminal connected to a first signal line GND via the select transistor; dummy cells DC disposed at the respective plurality of bit lines BL, and each including a resistance element R of a constant resistance value, the resistance element having one terminal connected to the bit line BL and the other terminal connected to a second signal line SIG; and a voltage sense amplifier SA connected to the plurality of bit lines BL.

Magnetic memory device and method for reading the same

An information processing apparatus that enables an undefined variable reference check on a dynamic variable. A dynamic variable specifying section specifies target dynamic variables from a source file. An area specifying section specifies areas ensured in the case of dynamic variables specified by the dynamic variable specifying section being developed into a memory at the time of executing a load module. An initializing section initializes areas specified by the area specifying section to a predetermined value.

Information processing apparatus

Prior to the first read operation for reading data from real memory cells, the second read operation for reading data from dummy memory cells is carried out using reference memory cells. A reduced residual dielectric polarization values of ferroelectric capacitors of the reference memory cells due to heat treatment and the like in manufacturing process, is recovered by the second read operation to an original value before the read access to the real memory cells. Therefore, data in the real memory cells is properly read out in the subsequent first read operation. As a result, it is possible to certainly read data from a ROM area in a ferroelectric memory to which data is written in advance in a test process of the manufacturing process, for example.

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Kawasaki, Japan

Masaki Aoki