Fujitsu Corporation

Masakazu Tanomoto

Hideki Okawara

Taisuke Saiki

Ryotaro Tokumaru

A cache control apparatus includes a data unit configured to store data on an index-specific basis, a tag unit configured to store, on the index-specific basis, a tag and a flag indicating whether the data has an uncorrectable error, and a control unit configured to refer to the flag, upon detecting a tag hit by performing a read access to the tag unit, to determine whether an uncorrectable error exists in the data corresponding to the tag hit, wherein the control unit performs process scheduling such that the read access to the tag unit and another access to the tag unit are performed simultaneously.

Cache control apparatus and cache system control method

An arithmetic processing device includes circuitry configured to add an identifier of a request source that generates a prefetch request into the prefetch request, and output, in response to detecting a certain number of cache hits less than a first threshold, each of the cache hits occurring in a first cache memory provided at a lower hierarchical level than a second cache memory by each prefetch request into which a first identifier is added, a notification for suppressing a prefetch request issued for the lower hierarchical level of the first cache memory from a first request source identified by the first identifier.

Arithmetic processing device and arithmetic processing method of controlling prefetch of cache memory

A TLB receives an access request with respect to a first address and access authorization assigned to the request from an arithmetic operation control unit, translates the first address to a second address, determines the suitability of the access authorization, and outputs the access request with respect to the first address when the access authorization is not suitable. An MMU receives the access request with respect to the first address output from the TLB, translates the first address to the second address, determines the suitability of the access authorization, and outputs a notification of access prohibition to the arithmetic operation control unit when the access authorization is not suitable.

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Kawasaki, Japan

Masakazu Tanomoto