Sony Computer Entertainment Inc.

Sony Corporation

International Business Machines Corporation

Sony Interactive Entertainment Inc.

Kabushiki Kaisha Toshiba

Other

Sony Corporation Entertainment Inc.

Sony Interactive Entertainment Europe Limited

Masaaki Oka

Masakazu Suzuoki

Masayoshi Tanaka

Makoto Furuhashi

Teiji Yutaka

Akio Ohba

Takeshi Yamazaki

Toyoshi Okada

Harm Peter Hofstee

Charles Ray Johns

James Allan Kahle

Shigehiro Asano

Ken Kutaragi

Atsushi Kunimatsu

Akiyuki Hatakeyama

Yuki Karasawa

Takahiro Fujii

Shuji Hiramatsu

Shigeru Enomoto

Tomokazu Kake

Muneki Shimada

Kenjiro Komaki

Martin Edward Hopkins

Yousuke Kimoto

Hiromasa Horie

Keiso Shimakawa

Yuta Kimura

Hidehisa Onai

Michael K Gschwind

Ravi Nair

Michael Norman Day

David Jones Craft

Sumedh Wasudeo Sathaye

Maximino Aguilar, Jr

Yukio Watanabe

John-David Wellman

Masakazu Hayashi

Erik Richter Altman

Norihiro Nagai

Toshiyuki Hiroi

Peter George Capek

Andrew James Bigos

Koji Kageyama

Toru Akazawa

Eiji Iwata

Richard James Forster

Yasuyuki Yamamoto

Kojiro Umemura

Neil Jonathan Brown

Joseph Charles Boulter

Jean-Paul Roberts

Neil Brown

Martin E Hopkins

With respect to a space including an objectof a display target, images of the space viewed from reference pointstoof view are created as reference images, andin advance and they are synthesized according to a position of an actual point of view to render a display image. In the certain reference image, data other than a partrepresented only in it is deleted. At the time of rendering of the deleted part, the other reference imagesandare used.

Freely selected point of view image generating apparatus, reference image data generating apparatus, freely selected point of view image generating method, and reference image data generating method

For a space including an object to be displayed, images of the space viewed from reference points of view are created in advance as reference images, and the reference images are combined according to a position of an actual point of view to draw a display image. In this case, a reference image not displaying reflection is used to determine the color of the object (S). In a case of expressing reflection of another object (Y in S), a position of the reflected object is estimated in a three-dimensional space (S), a position on the reference image corresponding to the position is acquired (S), and a color of the position is combined with the color of the object (S).

Image generation apparatus and image generation method

To achieve a balance between responsiveness of image display with respect to movement of a viewing point, and image quality. Reference viewing points are set in respect of a space containing an object to be displayed, and images of the space as viewed from these respective reference viewing points are created as reference images. Meanwhile, when pixel values of display images from a virtual camera are determined, reference images are selected wherein a point on the object represented by the pixel in question is represented as an image, and the values of these pixels are combined using a rule based on the positional relationship etc. of the reference viewing points with the virtual camera.

Image generating device and method of generating image

Aspects of the technology include method of selecting an object from a videogame for 3D printing. The method involves periodically rendering a virtual environment of a videogame for display at a succession of points in time. Information is periodically recorded that enables visual reconstruction of at least part of the virtual environment at a succession of points in time. A predetermined set of values is periodically recorded responsive to the state of the rendered virtual environment at a succession of points in time. The predetermined set of values enables a model of a selected part of the rendered virtual environment to be generated that is configured for 3D printing.

Device and method of selecting an object for 3D printing

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing tasks is also provided. The processing system includes processing devices and an absolute timer. The absolute timer defines a time budget. The time budget provides a time period for the completion of tasks by selected processing devices independent of clock frequencies employed by the processing devices for processing the tasks.

System and method for data synchronization for a computer architecture for broadband networks

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

Methods and apparatus provide for placing an apparatus into at least one of a plurality of operational modes, wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the local memory over the bus.

Methods and apparatus for secure data processing and transmission

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

Methods and apparatus provide for translating a software program page by page from a first instruction set architecture (ISA) into a second ISA using one or more of a set of processors of a multi-processor system; and executing the translated software program using a dedicated other processor of the multi-processor system.

Methods and apparatus for instruction set emulation

Methods and apparatus provide for: receiving a memory access request for data from a processor of a multi-processor system; determining whether the data of the memory access request is stored in a remote processing system coupled to the multi-processor system over a communications network; requesting the data from the remote processing system; receiving the data from the remote processing system over the communications network; and providing the data to the processor of the multi-processor system.

Methods and apparatus for virtualizing an address space

Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status information of the entry of the DMA table associated with the DMA data transfer to indicate that the DMA data transfer has been completed.

Methods and apparatus for hybrid DMA queue and DMA table

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

Computer architecture and software cells for broadband networks

Methods and apparatus provide for loading at least one software program module from a storage medium into a local memory of a processor for execution, the storage medium containing a main module and a plurality of sub-modules of the software program; and updating an address table, copies of the address table being located in at least one of the storage medium and the local memory, and the address table having at least one entry for each of the modules, each entry including at least one of: (i) a destination address representing an address within the local memory of a processor at which the corresponding module is disposed, and (ii) a source address representing an address within the storage medium at which the corresponding module originates.

Methods and apparatus for dynamic linking program overlay

A processing element (PE) includes a processing unit (PU) and a number of attached processing units (APUs). The instruction set of each APU is divided a priori into a number of types, each type associated with a different amount of heat generation. Each APU keeps track of the amount of each type of instruction executed over a time period, &#x2014;the power information, &#x2014;and provides this power information to the PU. The PU then performs power management as a function of the provided power information from each APU, &#x2014;such as directing a particular APU to enter an idle state to reduce power consumption.

Power management for processing modules

Growing community of inventors

Tokyo, Japan

Masakazu Suzuoki