At&t Bell Laboratories

Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Lucent Technologies Inc.

At+t Corp.

Agere Systems Guardian Corp.

Agere Systems Inc.

At&t Laboratories, Limited

Masakazu Shoji

Federico Capasso

Alfred Yi Cho

Deborah Lee Sivco

Donald E Blahut

Norman Loren Schryer

Veikko R Saari

Robert H Krambeck

Charles M Lee

Victor K Huang

Milan F Jukl

Thomas E Seidel

Susanta Sen

Frank E Barber

Robert M Rolfe

Jonathan A Fields

Michael S Chung

An operating parameter of an integrated circuit is made substantially insensitive to process variations by configuring the circuit such that an environmental parameter, e.g., supply voltage to a portion of the circuit, is made a function of one or more process parameters, e.g., conduction threshold voltages and mobilities in that portion of the circuit. In this manner, the effect of the process parameters on the circuit operating parameter may be partially or substantially offset by the effect of the process parameters on the environmental parameter. In an illustrative embodiment, the circuit operating parameter is an oscillation period of a ring oscillator. A voltage regulator generates a reference voltage which is determined at least in part based on known process parameter variations in the ring oscillator. The ring oscillator utilizes the reference voltage generated by the voltage regulator as its supply voltage, and its oscillation period is thereby made insensitive to the process parameter variations. In addition, back-bias effects may be introduced in the voltage regulator to compensate back-bias effects resulting from particular configurations of the ring oscillator. The design techniques of the invention may be applied to a wide variety of different types of integrated circuits, operating parameters, environmental parameters and process parameters.

Process-tolerant integrated circuit design

A method for creating signal unidirectionality in electronic circuits is disclosed. This invention describes a method for achieving unidirectionality in an electronic circuit with an input side having a signal source and an output side with a load comprising detecting the current passing through the load on the output side, bypassing a portion of the current passing through the load on the output side, and feeding the bypassed portion of the current on the output side to the input side to achieve unidirectionality. Specifically, unidirectionality in an electronic circuit is accomplished by applying feedback such that the impedance looking into the input of the amplifier is increased. These methods are particularly applicable to negative resistance amplifier circuits.

Unidirectionality in electronic circuits through feedback

Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The threshold voltages are determined by extrapolation from the (high) gate to source voltage. Each of the N-channel transistors is paired with a corresponding P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage equal to the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage.

Optimized low voltage CMOS operation

Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and second inverter chains, each having a plurality of series-connected inverters. A first signal, which may be a digital logic signal, is applied to an input of the first inverter chain. A second signal, which may be a clock signal used to latch the logic signal in an integrated circuit, is applied to an input of the second inverter chain. The inverter chains may be constructed such that the inverters of the second chain have a stronger drive capability than the corresponding inverters of the first chain. Capacitive coupling is provided between outputs of inverters of the first chain and outputs of corresponding inverters of the second chain. The capacitive coupling provides interaction between the first and second inverter chains which acts to align transition edges of the first and second signals as the signals propagate through the respective first and second inverter chains. The edge alignment process may be facilitated by intentionally reducing a transition rate of either the first or second signal. This intentional transition rate reduction could be provided by applying the first or second signal to a delay circuit at an input of the corresponding inverter chain, or by connecting additional capacitive loads to outputs of the first several inverters in the corresponding inverter chain.

Digital signal transition edge alignment using interacting inverter

A memory device and method of packaging to increase the production yield of large scale digital memory chips. The architecture provides the ability to house a plurality of partially defective memory chips into a single casing to provide the same memory as a non-defective chip, thus eliminating the need to discarding a chip having minor defects. The chips are divided into data blocks that can be individually tested and disabled so that only that defective block is discarded not the entire chip, thus increasing production yield.

Memory chip architecture and packaging method for increased production

A semiconductor memory device contains graphic information which is viewable both by direct, visual observation of the memory and electrically, e.g., via a TV screen. The device contains a semiconductor chip having a surface and an array of electrically addressable memory cells therewithin. A photograph is made on the chip for storing graphic information projected onto the chip. The photograph comprises pixels which themselves comprise variable value circuit elements of the cells, or which are optically coupled to cell circuit elements for controlling the values thereof in correspondence with the optical characteristics of the pixels. The circuit elements determine the memory content of the cells in correspondence with the graphic information stored in the photograph.

Semiconductor optical storage device and uses thereof

A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjunction with a data decoder. With this arrangement it is possible to store, at a single memory site, information that would have required up to .left brkt-top.log.sub.2 (n(n-1)/2)+1).right brkt-top. individual memory sites in a conventional ROM (where n is the number independent of bit-lines connected to an individual memory element in the invention). The invention is particularly well-suited to what would be considered relatively low-speed data retrieval systems, such as those adapted to provide audio and/or video to a user on a real time basis.

High-density read-only memory

A system and method for generating a signal having a reliable, fixed duration and/or delay as a function of relative, not absolute, device characteristics. That is to say, the time period of the generated signal is determined as a ratio of one device's operating characteristics to another device's operating characteristics. In particular, the invention provides a fixed time signal as a function of the relative values of two capacitive elements that have a known ratio of capacitance with respect to each other. The invention is particularly useful when implemented upon an integrated circuit, as standard fabrication techniques for such circuits allow relative device characteristics to be held to relatively tight tolerances.

Fixed-interval timing circuit and method

A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjunction with a data decoder. With this arrangement it is possible to store, at a single memory site, information that would have required up to log.sub.2 (n(n-1)/2)+1) individual memory sites in a conventional ROM (where n is the number independent of bit-lines connected to an individual memory element in the invention). The invention is particularly well-suited to what would be considered relatively low-speed data retrieval systems, such as those adapted to provide audio and/or video to a user on a real time basis.

High-density read-only memory employing multiple bit-line interconnection

The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per output. Each of the plurality of outputs is connected to one of a plurality of memory cells. Each memory cell comprises an impedance element, its impedance value representative of the data value stored therein. All of the memory cells are thereafter connected to a sum line and a read out circuit. When the signal source provides one of the sequence signals to one of the memory cell impedance elements, it affects the signal on the sum line in a manner that is related to the impedance value of the memory cell. By applying each signal in the sequence to a different impedance element, the voltage on the sum line is directly affected by each of the impedance elements in sequence. The read out circuit transforms the read out circuit voltage into a voltage level proportional or otherwise indicative of each impedance value, and thus the stored data, in sequence.

Integrated circuit memory device

A method for fabricating read-only memory ('ROM') devices utilizing junction field-effect transistors ('JFETs') having a conductive channel orthogonally oriented with respect to the surface of the semiconductor material composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source and drain contact. Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.

High-density read-only memory fabrication

Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local condition which is proportional to the local condition's effect on the active element and a compensation element which is coupled to the detecting element and to the portion for reacting to the response of the detecting element tot he local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the local condition's effect on the active element. An embodiment of the apparatus which compensates for leakage currents in FETs in a dynamic CMOS integrated circuit employs one or more FETs which are interspersed among active FETs as the detecting element and a current mirror as the compensating element. The current mirror responds to the leakage current in the detecting element FETs by producing a compensating current to compensate for the leakage current in the active FETs. The embodiment is employed in a dynamic NOR gate and a dynamic PLA.

Integrated circuits which compensate for local conditions

A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e.g., in apparatus designed for ternary logic operations, frequency multiplication, waveform scrambling, memory operation, parity-bit generation, and coaxial-line driving. The device can be made by layer deposition on a substrate and includes a resonant-tunneling structure between contacts such that side-by-side first and third contacts are on one side, and a second contact is on the opposite side of the resonant-tunneling structure.

Apparatus including resonant-tunneling device having multiple-peak

A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull-down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull-up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input.times.17 output CMOS digital crossbar switch can be made to operate with date rates as high as 300 megabits per second.

CMOS Integrated circuit digital crossbar switching arrangement

Integrated circuit chips with two (or more) multi-element logic paths--suffering from signal skew operation because of semiconductor processing variations--can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic path is approximately equal to the sum of the pull-up delays in the other logic path (or in each of the other logic paths) and such that the sum of all the delays (pull-down plus pull-up) in one path is substantially equal to the sum of all the delays in (each of) the other(s)--all in response to an input signal transition (low to high, high to low, or both) applied to each path.

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Warren, NJ, United States of America

Masakazu Shoji