Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Masakazu Kakumu

Sigeru Morita

Kazutaka Nogami

Takeo Maeda

Masaaki Kinugawa

Tetsuya Asami

Hisao Yoshimura

A plurality of silicon insulating films are formed to separate regions to be formed with elements from each other on a silicon semiconductor substrate. Silicon layers are formed by an epitaxially growing method on the regions to be formed with the elements and the silicon insulating film. An MOS transistor is formed on the monocrystalline silicon layer formed on the regions to be formed with the elements of the silicon layer, and the polysilicon layer formed on the silicon insulating film is used as a high resistance element or doped with an impurity as a conductor line.

Semiconductor device and a method for manufacturing the same

In a semiconductor device, an n.sup.+ -type polysilicon layer is formed on a substrate through a gate oxide layer. A p.sup.+ -type source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The n.sup.+ -type polysilicon layer is positioned over an intermediate portion of a channel formation layer, and has an oxide layer on an upper surface thereof. The n.sup.+ -type polysilicon layer has at its side portions a p.sup.+ -type polysilicon layer to make a gate electrode together with the n.sup.+ -type polysilicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in such a manner that in a portion contacting with the gate insulation layer, the nearer the portion approaches the impurity layers of the source and drain regions, the larger the work function of the portion becomes.

Method of manufacturing MOS-type semiconductor device having electrode

In a method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region, thereby forming metal silicide layers of low resistance on only the diffusion layers. In a further method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region and the upper surface of a gate electrode. Then, the structure is subjected to a process to make a silicide, thereby forming metal silicide layers of low resistance on only the diffusion layers and the gate electrode.

Method for manufacturing a semiconductor device having reduced

A semiconductor device comprising a main circuit having a p-channel MOSFET formed on the surface off the substrate and an n-channel MOSFET formed on the p-type well region which is formed on the n-type Si substrate chip), an input/output (I/O) circuit formed on the substrate, and a substrate bias generating circuit formed on the substrate, characterized by controlling the substrate bias generating circuit via the I/O circuit, and varying a bias supplied to the substrate and the p-type well region, in accordance with the operation mode of the main circuit.

Semiconductor device

A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions. The depth of the third well region is such that a depletion layer extending below the gate electrode (5) of the PMOS FET can be connected to a depletion layer formed at the interface between the third and fourth well regions.

Semiconductor integrated circuit device having double well structure

In a semiconductor device, an n.sup.+ polysilicon layer is formed on a substrate through a gateoxide layer. A p.sup.+ source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The silicon layer positions over an intermediate portion of a channel formation layer, and has an oxide layer on upper surface thereof. The silicon layers have their side portions a p.sup.+ type polysilicon layer to be a gate electrode together with the silicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in the manner that, in a portion contacting with the gate insulation layer, the nearer portions approaches to the impurity layers of the source and drain regions, the larger a work function increases.

MOS-type semiconductor device having electrode structure capable of

A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first impurity region of second conductivity which is formed in the substrate, a second impurity region of the second conductivity type which is formed in the substrate and spaced apart from the first semiconductor region, a channel region located between the first and second impurity regions, an insulation layer on the channel region, and a gate electrode on the insulation layer including conductive layer means for decreasing the temperature dependence of the semiconductor device, the layer means including a conductive layer and a semiconductive layer for reducing energy level degeneration.

Semiconductor device FET with reduced energy level degeneration

A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, forming a high impurity concentration layer of a second conductivity type in the surface area of a portion of the semiconductor substrate defined by the element isolation region, and forming a first insulation film on the entire surface of the resultant semiconductor structure. Thereafter, a contact hole is formed in the first insulation film which is formed on the high impurity concentration layer, a semiconductor layer containing an impurity of the same conductivity type as the high impurity concentration layer is formed on the first insulation film, and a second insulation film is formed on the semiconductor layer. After this, a planarization film is formed on the entire surface of the second insulation film and is then selectively removed by anisotropic etching, to leave part of the planarization film filling the contact hole. Then, the portion of the planarization film exposed by the anisotropic etching is removed, a metal layer is formed on the entire surface of the resultant semiconductor structure, and the metal layer and semiconductor layer are patterned to form a laminated structure of a wiring layer.

Method for forming contact portion in semiconductor integrated circuit

A semiconductor manufacturing method which comprises the steps of forming a polycrystalline silicon layer on a semiconductor substrate; depositing a silicon oxide layer on the polycrystalline silicon layer; mounting an acidproof layer on the silicon oxide layer; selectively eliminating the acidproof layer deposited on a semiconductor element-isolating region by the photoetching process; selectively eliminating the silicon oxide layer with the retained acidproof layer used as a mask; ion implanting a channel stopper impurity in the semiconductor substrate through the masks formed of a photoresist coated on the acidproof layer the acidproof layer, and silicon oxide layer; eliminating the photoresist; selectively depositing a silicon layer on the exposed polycrystalline silicon; carrying out thermal oxidation with the acidproof layer used as a mask; eliminating the acidproof layer; filling an oxide in the cavities of the side walls of the semiconductor element-isolating insulation layer; and exposing by etching that portion of the semiconductor substrate which will constitute a semiconductor element region, thereby forming a thick semiconductor element-isolating layer with high precision in a narrow semiconductor element-isolating region.

A method of manufacturing semiconductor elements-isolating silicon oxide

A method of manufacturing a semiconductor substrate, and, in particular, a technique of electrically isolating a semiconductor element formed on a semiconductor substrate. The method comprises the steps of depositing a silicon oxide layer on the surface of a silicon substrate, for its protection; forming a silicon nitride layer on the silicon oxide layer; selectively eliminating the silicon nitride layer; oxidizing the silicon substrate, with the retained silicon nitride layer being used as a mask, thereby providing an oxide layer; depositing a polycrystalline silicon layer on the oxide layer and the retained acid-resisting layer; oxidizing the polycrystalline silicon layer to provide an insulation layer; eliminating the insulation layer until the silicon nitride layer is exposed; and removing all the silicon nitride layer. The method is capable of enabling the formation of a thick semiconductor element-isolating oxide layer, with a high precision, in a narrow region from which the semiconductor element is to be isolated.

Method of increasing the thickness of a field oxide

In a method of forming electrodes or wiring structures in a semiconductor device, metal and metal silicide are used for electrodes and lead wires, impurities are doped into the interface of a semiconductor substrate from the surface by gas diffusion or solid diffusion irrespective of the thickness, and in the case where the base material is an insulating material, the impurities are not doped into the semiconductor region side by self-alignment.

Growing community of inventors

Kawasaki, Japan

Masakazu Kakumu