Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Other

Hitachi Industrial Equipment Systems Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Denshi Kabushiki Kaisha

Hitachi Tohbu Semiconductor, Ltd.

Semiconductor Technology Academic Research Center

Vlsi Engineering Corporation

Hitachi, Ltd., Hitachi Vlsi Engineering Corporation

Masakazu Aoki

Masashi Horiguchi

Kiyoo Itoh

Takeshi Sakata

Yoshinobu Nakagome

Jun Etoh

Takayuki Kawahara

Hitoshi Tanaka

Kunio Uchiyama

Hiromasa Noda

Kan Takeuchi

Iwao Takemoto

Youji Idei

Kazuhiko Kajigaya

Shinya Ohba

Kazuo Yano

Takashi Hashimoto

Ryoichi Hori

Osamu Nagashima

Tomoyuki Ishii

Koichi Seki

Haruhisa Ando

Masaharu Kubo

Shinichi Ikenaga

Katsuhiro Shimohigashi

Kazumasa Yanagisawa

Akira Suzuki

Masaaki Nakai

Shin'ichi Ikenaga

Ryoichi Kurihara

Toshifumi Ozaki

Natsuki Kawabata

Shoji Hanamura

Katsumi Matsuno

Ryuichi Izawa

Takaaki Noda

Koichiro Ishibashi

Masanao Yamaoka

Shoji Shukuri

Goro Kitsukawa

Toshio Sasaki

Junichi Nishimoto

Kazuaki Shiinoki

Hirotaka Kameya

Kiyoshi Inoue

Tomonori Sekiguchi

Shinichiro Kimura

Toshio Sugano

Yoshiki Kawajiri

Takesada Akiba

Toshiaki Masuhara

Osamu Minato

Hiroyuki Matsuda

Norio Koike

Hitoshi Nishimura

Hideyuki Aoki

Seiichiro Tsukui

Koji Kawamoto

Takao Watanabe

Toshio Nakano

Takuya Imaide

Kazuyoshi Oshima

Tsugio Takahashi

Masayuki M Nakamura

Akira Sasano

Hideo Nakamura

Yoshitaka Tadaki

Katsuyuki Sato

Osamu Tsuchiya

Yuji Yatsuda

Kanji Oishi

Shigeru Machida

Hidetoshi Iwai

Makoto Hanawa

Masahiko Takano

Kenji Takahashi

Toshihiro Sekiguchi

Masanobu Miyao

Hiroshi Kawamoto

Jun Murata

Yasushi Kawase

Toshikazu Tachibana

Fumio Takeda

Shigekazu Nozawa

Masao Tamura

Manabu Tsunozaki

Yoshio Taniguchi

Tetsu Udagawa

Tatsuo Natori

Katsuaki Takagi

Makoto Saeki

Yoshitaka Kinoshita

Toshiaki Yabe

Masayuki Urashin

Takeshi Hida

Masakazu Hase

Kyoko Ishii

Shigeki Ueda

A high reliability water injected scroll air compressor is provided with an orbiting scroll, a fixed scroll corresponding to the orbiting scroll, a motor that generates driving force for making the orbiting scroll orbit the fixed scroll, a compressing path from a suction port to a discharge port, and a portion for injecting water into the compressing path. The operation is controlled by a switching operation in which water is injected into the compressing path and then no water is injected. Corrosion, failure of activation, and concerns about wrap contact when water is injected into an air end are avoided by switching the operation with water injection and the operation without water injection so as to prevent water from remaining in the air end.

Water injected scroll air compressor

A water-injected compressor, which injects the water inside the separatorinto the compressor and discharges the water along with compressed air into the separator and then gains condensed and separated water, has the compressor stopping and then, if staying at a stop for a predetermined duration of time without activating, becoming activated and operating for a set duration of time.

Water-injected compressor

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Semiconductor element and semiconductor memory device using the same

To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

Semiconductor integrated circuit device

Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit

An oil injected screw compressor has an oil separating mechanism integrated with a compressor and hence is made compact in size. A male rotor and a female rotor are received in a rotor casing. The shafts of these rotors are arranged substantially in a horizontal direction. An inner cylindrical wall is arranged under the rotor casing with its center axis arranged substantially in a vertical direction and an outer wall is arranged substantially in a concentric position with the inner wall. A lower casing is hermetically joined to the outer wall. Oil in the working gas which is injected in the compression process of the oil injected screw compressor is primarily separated from the working gas between the inner wall and the outer wall. The primarily separated working gas flows up inside the inner wall and is guided through a manifold into an oil separating element case where the oil is secondarily separated from the working gas.

Oil injected screw compressor

A semiconductor integrated circuit device is composed of logic gates each provided with MOS transistors. The semiconductor integrated circuit device includes a current control device. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors, that have both an operation mode and a low power back-up or sleep mode used for power reduction.

A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Semiconductor device having redundancy circuit

On a basic measurement unit arranged in a lattice shape on a chip, a resistance measurement circuit, a capacity measurement circuit, an n-type MOS transistor measurement circuit, a p-type MOS transistor measurement circuit, and a ring oscillator measurement circuit are mounted by several tens of patterns. Each measurement circuit mounted by several tens of patterns is connected to a measurement bus to constitute a measurement bus net in accordance with measured items. Switching of connection of the measurement bus net with a measurement terminal pad is electrically controlled properly by X, Y address selection signals outputted from X, Y address decoders to X, Y address selection signal lines.

Semiconductor characteristic evaluation apparatus

Growing community of inventors

Tokorozawa, Japan

Masakazu Aoki