Adv Antest Corporation

Masakatsu Suda

Toshiyuki Okayasu

Satoshi Sudou

Takuya Hasumi

Shusuke Kantake

Masahiro Ishida

Daisuke Watanabe

Kazuhiro Fujita

Kosuke Ikeda

Katsuhiko Degawa

Tasuku Fujibe

Kengo Suzuki

Yushi Nishino

Koichi Tanaka

Takahiro Yamaguchi

Shinya Sato

Kazuhiro Yamamoto

Shoji Kojima

Mitsuo Matsumoto

Masayuki Kawabata

Satoshi Iwamoto

Shuusuke Kantake

Yoshihito Nagata

Provided is a measurement apparatus including a signal source configured to output a binary digital signal configuring a multi-tone waveform, a waveform acquisition unit configured to acquire an analog signal waveform generated in response to application of the digital signal to a device under test, and a computation unit configured to calculate a frequency characteristic of the device under test from the waveform acquired by the waveform acquisition unit, in which the signal source is configured to repeatedly output a signal upconverted by multiplying a pseudo-random binary sequence (PRBS) signal by a repeating rectangular wave with a reference frequency and a reference duty ratio.

Measurement apparatus, measurement method and computer readable medium

An authentication system comprising an authentication terminal and an authentication server is provided. The authentication terminal comprises an authentication apparatus authenticating an authentication subject, an artifact operating in accordance with an input signal and a signal processing section inputting an input signal without including information of the authentication subject designated by the authentication server in the artifact and outputting an output signal in accordance with an operation result of the artifact as an authentication result when the authentication result in the authentication apparatus is passed. The authentication server authenticates the authentication subject based on the output signal.

Authentication system, authentication method and service providing system

An authentication terminal comprising an authentication apparatus authenticating an authentication subject, an artifact operating in accordance with an input signal and a signal processing section is provided. When an authentication result in the authentication apparatus is passed, the signal processing section inputs an input signal without including information of the authentication subject in the artifact and outputs an output signal in accordance with an operation result of the artifact as the authentication result.

Authentication terminal

A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.

Semiconductor circuit with load balance circuit

A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.

Clock hand-off circuit

A timing generator that outputs a timing signal obtained by delaying an input signal, comprising first and second period delay sections that each output a rate signal obtained by delaying the input signal by a delay amount corresponding to an integer multiple of a period of an operation clock supplied thereto; a first high-accuracy delay section that outputs the timing signal obtained by delaying a signal input thereto by a delay amount that is less than the period of the operation clock; and a mode switching section that switches between a low-speed mode, in which the rate signal output by the first period delay section is input to the first high-accuracy delay section, and a high-speed mode, in which a signal obtained by interleaving the rate signals output by the first period delay section and the second period delay section is input to the first high-accuracy delay section.

Timing generator and test apparatus

A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information.

Apparatus for manufacturing substrate for testing, method for manufacturing substrate for testing and recording medium

There is provided a signal output apparatus for outputting a pattern signal. The signal output apparatus includes a pattern generating section that generates waveform data of the pattern signal to be generated, a timing generating section that generates timing signals in accordance with an expected pattern cycle time of the pattern signal, a timing control section that receives the waveform data output from the pattern generating section, and controls output timings of the timing signals to be output from the timing generating section, in accordance with the waveform data, and a waveform shaping section that generates the pattern signal corresponding to data values of the waveform data output from the pattern generating section, in accordance with the timing signals output from the timing generating section.

Signal generation and detection apparatus and tester

A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.

Loop type clock adjustment circuit and test device

A delay lock loop circuit and its delay amount calibration method is disclosed. An initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and based on the reading, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. If any cycle slip is not caused, the counter set value is locked, thereby terminating the process.

Delay lock loop circuit, timing generator, semiconductor test device, semiconductor integrated circuit, and delay amount calibration method

A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.

Delay circuit, test apparatus, storage medium semiconductor chip, initializing circuit and initializing method

Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that judges whether the device under test is defective or not, based on an output signal outputted from the device under test; a power supply apparatus that supplies a source power to the device under test; and a setting section that detects a fluctuation amount of the source voltage resulting when the test pattern is inputted to the device under test, and sets, based on the detected fluctuation amount, a current range within which a compensation current that is in accordance with a fluctuation of a consumption current consumed by the device under test is generated at a predetermined number of levels so as to compensate a fluctuation of a source voltage to be applied to the device under test attributable to the fluctuation of the consumption current.

Test apparatus, test method and computer readable medium

A variable delay circuit is designed to provided a wider range of delay time to a timing signal. The variable delay circuit includes a variable delaywhich comprises a DA converterwhich supplies currentbased on delay setting data; a delay elementwhich imparts a delay amount Tpd to a prescribed signal and outputs the signal; and a bias circuitwhich is connected such that the amount of current flown in the DA converterand the amount of current flown in the delay elementbecome equal. The DA converterallows the relationship between the delay setting data DATA and the current Id to be hyperbolic (inversely proportional). As a result, the relationship between the delay setting data DATA and the delay amount Tpd can be linearized, whereby the delay amount obtained by a single stage of the delay element can be increased.

Variable delay circuit, timing generator and semiconductor testing apparatus

A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuitfor distributing the clock to timing generating sections-to-n has a clock main pathconnected to a main path bufferand a clock return pathconnected to a return path buffer. A load capacity of the main path bufferis equal to that of the return path buffer. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.

Timing generator and semiconductor test apparatus

A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.

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Tokyo, Japan

Masakatsu Suda