Sony Corporation

Masakatsu Nakai

Takahiro Seki

Tetsumasa Meguro

Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate.

Semiconductor device having a power cutoff transistor

A semiconductor apparatus for flexibly and effectively configuring a delay monitor circuit without an increase in circuit scale includes a delay signal generation circuit for switching the configuration of delay element arrays based on first configuration information and second configuration information and propagating a delay element array wherein a pulse is switched, a register group having a first register for the first configuration information and a second register for second configuration information, a selector for outputting to the delay signal generation circuit the first configuration information and second configuration information in accordance with an instruction of a selection signal in a time sharing way, and a control circuit for controlling a power source voltage based on delay information of a delay element array and outputting to the selector a selection signal to select from the first configuration information and second configuration information in a time sharing way.

Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit

A semiconductor chip able to reduce wasteful power loss due to a margin of power supply voltage considering variation of characteristics. A voltage setting signal for setting the power supply voltage to be supplied to a target circuit is generated in a voltage controller in the semiconductor chip based on a delay time of a delay signal of a replica circuit with respect to a clock signal. The maximum value of power supply voltage set by the voltage setting signal is restricted to the maximum value of the power supply voltage determined based on variations in production of the semiconductor chip. Accordingly, even when the value of the power supply voltage set based on the delay signal exceeds the maximum value due to the margin set considering the variation of characteristics, the voltage setting of the voltage setting signal output to the external power supply is restricted to the maximum value, so wasteful power loss can be suppressed.

Semiconductor chip

The present invention provides a semiconductor device a comprising: a delayed-signal-generating circuit for delaying a reference pulse signal by a delay time caused by a delay component on a critical path of a target circuit by a selector included in the delayed signal generating circuit and, thereby, generating a delayed pulse signal; a detection-signal-generating circuit, having the same delay component as the selector, for generating a detection pulse signal delayed in phase by one cycle of a clock signal Ck with respect to the reference pulse signal; a delay-difference-detecting circuit for detecting a phase difference between the delayed pulse signal and the detection pulse signal; and a control circuit for adjusting the magnitude of a power-supply voltage VDD supplied to the target circuit according to the-phase difference detected by the delay-difference-detecting circuit.

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Kanagawa, Japan

Masakatsu Nakai