Kabushiki Kaisha Toshiba

Masaji Ueno

Yasukazu Noine

Kumi Ofusa

Hiroyuki Hara

Tomohiro Ando

Hajime Shiraishi

Hideaki Masuoka

Akihito Nishikawa

Nobuo Koide

Shinichi Iida

According to an embodiment, the threshold value generation unit generates a setting voltage and converts the setting voltage to a first current. One end of the first resistor is connected to a detection terminal. When a voltage applied to the detection terminal is greater than or equal to a predetermined factor times the voltage of the higher voltage source, the detection unit causes a constant detection terminal input current to flow from the detection terminal to the first resistor. When the voltage at the detection terminal is less than the predetermined factor times the voltage of the higher voltage source, a higher voltage source voltage is outputted to a detection output terminal, while the voltage at the detection terminal is greater than or equal to the predetermined factor times the voltage of the higher voltage source, a lower voltage source voltage is outputted to the detection output terminal.

Voltage detection circuit, ECU, automobile with ECU

A first control switch is connected between a first terminal to which one terminal of a first boosting capacitor element is connected and a supply node of an input voltage. A second control switch is connected between a second terminal to which the other terminal of the first boosting capacitor element is connected and the supply node of the input voltage. A first switch element is connected between a third terminal to which one terminal of a second boosting capacitor element is connected and at which an output voltage is generated and the first terminal. A second switch element is connected between a node of a reference voltage side of the input voltage and the second terminal. A control circuit detects the output voltage and controls the first and second control switches to obtain the desired output voltage on the basis of a detection result.

Booster power supply circuit that boosts input voltage

According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Hysteresis comparator

According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.

Output circuit and liquid crystal display device

An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.

Output buffer circuit

A semiconductor integrated circuit includes first and second differential amplification devices to amplify a voltage difference of input signals inputted from a positive input terminal and a negative input terminal, first and second addition devices to add an output of the first differential amplification device and the output of the second differential amplification device, an output stage control device controlled by the first and second addition devices, and output stage controlled by the output stage control device, and an output terminal connected to the output stage.

Semiconductor integrated circuit

The chip size of the high breakdown voltage push-pull output circuit for the semiconductor device can be reduced by use of only the low breakdown voltage transistor elements. Between the voltage supply terminal HVCC and the ground terminal GND, the control transistor element (Q1) and the voltage transistor element (Q3) are connected in series and stacked vertically. In the same way, the voltage transistor element (Q4) and the control transistor element (Q2) are connected in series and stacked vertically. Further, the output terminal (OUT) is derived from between the voltage transistor element (Q3) and the voltage transistor element (Q4). The supply voltage of 12V supplied through the voltage supply terminal HVCC is divided as voltages of 6V by the bias circuit BI, and then supplied to the bases of the two voltage transistor elements (Q3 and Q4), respectively. When the output is low, the supply voltage of 12V is divided 1/2 by the control transistor element (Q1) and the voltage transistor element (Q3). On the other hand, when the output is high, the supply voltage of 12V is divided 1/2 by the voltage transistor element (Q4) and the control transistor element (Q2). Therefore, it is possible to construct a push-pull circuit with a high breakdown voltage by use of only the low breakdown voltage transistor elements.

High breakdown voltage push-pull circuit for semiconductor device

A CMOS level converter including two CMOS inverter that are complimentary coupled with each other. Each of the CMOS inverter includes two MOS transistors and is coupled between a source voltage and a ground potential in series. When an input signal begins to change from a low level to a high level, one of the MOS transistors in an input side CMOS inverter is turned off, and the inverter is coupled through a diode to the ground potential. As the input level rises gradually, on the input side inverter, due to a high level output from an output side inverter, the MOS transistor turns on. As a consequent, the output is set at the ground potential in the level conversion, even when the amplitude is insufficient.

Level converter

A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off. The circuit further includes a device for restricting current flow from the output terminal to the predetermined potential side through the first and second transistors.

Low-voltage output circuit for semiconductor device

An output circuit has a bipolar transistor circuit of a 1st and a 2nd bipolar transistor connected in Darlington configuration. The base of the 1st transistor is supplied with an input signal. The collector of the 2nd transistor is connected to a power supply through a 1st diode. And, a signal is outputted from the emitter of the 2nd transistor. The output circuit also includes a 1st PMOS transistor. The source of the 1st PMOS transistor is connected to the base of the 2nd transistor, its drain being grounded, and its the backgate being connected to the power supply through the 1st diode. The output circuit may further includes a 2nd PMOS transistor having a source and a backgate both connected to the power supply, a drain connected to the base of the 2nd transistor through a second diode, and a gate supplied with an inverting signal of the input signal. The output circuit may further includes: a 2nd PMOS transistor connected between the drain of the 1st PMOS transistor and ground, having a source and a backgate both being grounded, a drain connected to the drain of the 1st PMOS transistor, and a gate supplied with the input signal; and a 3rd bipolar transistor having a base connected to the drain of the 1st PMOS transistor, a collector connected to the base of the 2nd transistor, and an emitter being grounded.

Output circuit in Darlington configuration

In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi. at two output terminals 4 and 5.

In-phase signal output circuit, opposite-phase signal output circuit,

A driver circuit suitable for use to secure output characteristics higher than the element breakdown voltage in an output circuit. The driver circuit includes first and second switching elements connected between a first supply voltage and an outward terminal for driving a load, a relaxation voltage applying section for applying a voltage lower than the first supply voltage to a junction point between the first and second switching elements and a back gate of the second switching element, and a control section for turning on the second switching element and then the first switching element in sequence when the driver circuit is turned on, and turning off the first switching element and then the second switching element in sequence when the driver circuit is turned off.

Output driver circuit with high breakdown voltage

It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.

Network interface system

A phase comparator has a switching circuit controlled by a switch signal and a phase comparing unit. The switching circuit receives a reference pulse signal having a duty ratio of 50% and a reception data signal having a duty ratio of less than 50%. One of these signals is selected by the switching circuit on the basis of control of the switch signal. The selected signal and an output signal from a voltage-controlled oscillator are supplied to the phase comparing unit. The phase comparing unit compares phases of the two signals. When the phase of the output signal from the voltage-controlled oscillator lags behind the phase of the selected reference pulse signal or reception data signal, the phase comparing unit outputs a first pulse signal, having a width corresponding to a phase difference between the two signals, for advancing the phase of the output signal from the voltage-controlled oscillator. When the phase of the output signal from the voltage-controlled oscillator leads ahead of the phase of the selected reference pulse signal or reception data signal, the phase comparator outputs a second pulse signal, having a width corresponding to a phase difference between the two signals, for delaying the phase of the output signal from the voltage-controlled oscillator.

Phase comparator having two different phase comparison characteristics

An output circuit for obtaining stable rising and falling characteristics regardless of variations in threshold voltages of output transistors. The output circuit obtains such favorable characteristics by using input signals changing in a complementary manner, a first MOS transistor which outputs a high potential level signal in response to a drive signal, and an output terminal for receiving the high potential level signal. In addition, the output circuit contains a drain-current control connected to a gate-source path for maintaining a drain current at a predetermined value, a second MOS transistor connected to a gate-source path which sets the output terminal at a ground level when it is turned on, and a second drain current control connected to a gate source of the second MOS transistor for maintaining a drain current at a predetermined value.

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Kanagawa-ken, Japan

Masaji Ueno