Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Masaitsu Nakajima

Takeshi Kishida

Takao Yamamoto

Tetsuya Tanaka

Shinji Ozaki

Hiroyuki Morishita

Ryuta Nakanishi

Hazuki Okabayashi

Keisuke Kaneko

Nobuo Higaki

Tokuzo Kiyohara

Hiroshi Kadota

Tadashi Okamoto

Masahide Kakeda

Tetsu Hosoki

Tomochika Kanakogi

Takao Kawakami

Yousuke Kudo

A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

Processor apparatus and multithread processor apparatus

A data processor includes a first register file including registers, a second register file including registers, a number of which is larger than that of the registers of the first register file, an instruction decoder and an operation unit. The instruction decoder decodes an instruction described in first and second instruction formats. The first instruction format includes a first register-addressing field for designating the first register file. The second instruction format includes a second register-addressing field for designating the second register file, a size of which is larger than that of the first register-addressing field. The operation unit executes an instruction described in the first and second instruction formats using operand data stored in the first and second register files, respectively, based on the instruction decoder, and executes operations in parallel, a number of which is determined by a certain field included in the second instruction format.

Data processor including an operation unit to execute operations in parallel

A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Method for instructing a data processor to process data

Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

Multithreaded processor

A processing device included on a single chip includes processors capable of executing tasks in parallel and a cache memory shared by the processors, wherein the cache memory includes single-port memories and read data selection units, each of the single-port memories have one data output port, and each of the read data selection units is in a one-to-one association with each of the processors and selects a single-port memory which stores data to be read to a associated processor, from among the single-port memories.

Processing device, computer system, and mobile apparatus

A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Parallel caches operating in exclusive address ranges

A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

Cache memory system, and control method therefor

In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

External device access apparatus

A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

Data processor decoding instruction formats using operand data

Data processor

Method and apparatus for arithmetic operation

A compiler is adapted to minimize the ultimate code size of an object program that has been translated from a source program including a plurality of instructions. The compiler includes first instruction length calculator for calculating a total length of the instructions where variables for the source program are allocated to a first type of register resources in accordance with a first instruction format and second instruction length calculator for calculating a total length of the instructions where the variables are allocated to a second type of register resources in accordance with a second instruction format. The length of one instruction defined by the second instruction format is different from that defined by the first instruction format. The variables are allocated to respectively appropriate ones of the register resources based on the results of calculation derived by the first and second instruction length calculators.

Growing community of inventors

Osaka, Japan

Masaitsu Nakajima