Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electronic Co., Ltd.

Masahito Otsuki

Seiji Momota

Hiroki Wakimoto

Tatsuya Naito

Katsunori Ueno

Akira Nishiura

Mitsuaki Kirisawa

Takashi Yoshimura

Koh Yoshikawa

Masaharu Nishiura

Tadashi Miyasaka

Takashi Shiigi

Noriho Terasawa

Tomoyuki Yamazaki

Shigeyuki Obinata

Ken'ya Sakurai

Tatsuhiko Fujihira

Yuichi Onozawa

Yasuyuki Hoshi

Akimasa Kinoshita

Yasuhiko Onishi

Michio Nemoto

Yukio Yano

Shoji Yamada

Ryu Saito

Ryu Saitoh

On a front surface of an n-type SiC substrate becoming a drain region, an n-type drift layer, a p-type base layer, and an n-type source layer are sequentially formed by epitaxial growth. In the n-type source layer, the p-type contact region is selectively provided. A trench is provided penetrating the n-type source layer and the p-type base layer in the depth direction and reaching the n-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 &#x3bc;m or less. A depth of the trench is, for example, 1 &#x3bc;m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Semiconductor device

In a semiconductor device, an IGBT and an SJMOSFET connected in parallel have respective gate terminals controlled independently of each other. When a high voltage occurs and a high current flows caused by short-circuit in an external circuit under a condition of ON state of the IGBT and SJMOSFET, an operational amplifier in the control IC detects the overcurrent through the IGBT and controls the gate signal to restrict the current through the IGBT. After that, the operational amplifier throttles the current through the IGBT according to a reference voltage of a capacitor decreasing by the discharge through a constant current source, thus conducting soft-OFF operation of the IGBT.

An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.

Semiconductor device and semiconductor device manufacturing method

To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT element; a super junction transistor element connected in parallel with the IGBT element; and a limiting section that limits a voltage applied to a gate terminal of the IGBT element more than a voltage applied to a gate terminal of the super junction transistor element.

A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p-type region constituting an edge termination structure provided in the flat portion.

In order to realize an SJ-MOSFET and an IGBT on a single chip and realize a new arrangement configuration for an SJ-MOSFET section and an IGBT section in a single semiconductor chip, provided is a semiconductor device including a semiconductor substrate; two or more super-junction transistor regions provided on the semiconductor substrate; and one or more IGBT regions that are provided in regions sandwiched by the two or more super-junction transistor regions, in a cross section obtained by cleaving along a pane perpendicular to the semiconductor substrate.

A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Vertical and trench type insulated gate MOS semiconductor device

A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

Power semiconductor device

A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number Nof p-type base regions that are connected electrically to the emitter electrode and the number Nof p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25&#x2266;{N(NN)}&#xd7;100&#x2266;75.

Insulated gate semiconductor device

A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25&#x2266;{N1/(N1+N2)}&#xd7;100&#x2266;75.

A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N -type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n -type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n -type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.

A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n drift layer is formed on an n cathode layer by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Power semiconductor rectifier with ring-shaped trenches

A semiconductor device constituting an IGBT exhibits low losses yet can be manufactured using an inexpensive wafer and with high yields, and exhibits low losses. The IGBT is produced by using a wafer, for example an FZ wafer, that is cut form an ingot and has its surface polished and cleaned, wherein an n-type impurity diffusion layer having an enough dose to stop the electric field in turn-off is provided between a collector layer and a base layer as a field-stop layer for stopping an electric field in turn-off. The thickness of this field-stop layer defined by Xfs&minus;Xj is controlled in the range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer is twice the impurity concentration of the base layer, and Xj is the position of the junction between the filed-stopping layer and the collector layer.

A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with an aqueous chemical solution to remove particles. To the cleaned surface, phosphorus ions arc implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300&deg; C. to 550&deg; C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.

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Matsumoto, Japan

Masahito Otsuki