Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Ericsson Mobile Communications Japan, Inc.

Masahisa Tamura

Takeshi Matsubara

Atsushi Yoshizawa

Ken Yamamoto

Hidenori Takeuchi

Hironori Nakahara

Shunsuke Sakazume

Tuan Van Pham

Provided are a semiconductor integrated circuit and an imaging device capable of reducing power consumption without complicating a configuration of oscillation control. A semiconductor integrated circuit includes an oscillator that generates an oscillation signal whose oscillation frequency is discretely adjustable on the basis of a digital control input signal, an oscillation controller that generates the digital control input signal, and an intermittent controller that generates an intermittent control signal and supplies the intermittent control signal to the oscillation controller so that the oscillation controller intermittently updates the digital control input signal.

Semiconductor integrated circuit

The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area. The phase locked loop includes: a digitally controlled oscillation unit that controls an oscillation frequency by a control signal in a digital format; a multiphase clock generation unit that generates clock signals with multiple phases synchronized with the digitally controlled oscillation unit; a clock selection unit that selects a selected clock signal out of the clock signals with multiple phases; a time-to-digital conversion unit that detects a time difference between the selected clock signal and a reference clock signal; a counter unit driven by any one clock signal out of the clock signals with multiple phases; a reference phase generation unit that generates a reference phase; a phase comparison unit that compares feedback phase information obtained from an output value of the counter unit and an output value of the time-to-digital conversion unit with the reference phase; and a digital loop filter unit that smooths output of the phase comparison unit and generates the control signal for the digitally controlled oscillation unit.

Phase locked loop and control method therefor

A semiconductor device includes: a first signal generation section configured to generate an activation signal having a variable duty ratio; and a first processing section configured to perform intermittent operation, based on the activation signal.

Semiconductor device and method of controlling the same

An oscillator circuit includes: an arithmetic section configured to correct a first input code value and thereby generate a first code value that is within a first predetermined range, the arithmetic section being configured to correct a second input code value in correspondence with a correction amount of the first input code value and thereby generate a second code value, and the first predetermined range being narrower than a range of the first input code value; and an oscillation section configured to generate an oscillation signal having a frequency that varies at first sensitivity based on the first code value and varies at second sensitivity based on the second code value, the second sensitivity being higher than the first sensitivity.

Oscillator circuit and frequency synthesizer

An electronic circuit includes a plurality of delay elements configured to delay a clock signal by a delay time and to supply the delayed clock signal as a delay signal, the delay time being shorter with a higher power source voltage; a delay time acquisition unit configured to acquire the delay time based on a value of the delay signal; and a voltage controller configured to perform a voltage control process in which the power source voltage is controlled to be high in a case where the acquired delay time is longer than a predetermined desired value and the power source voltage is controlled to be low in a case where the acquired delay time is shorter than the predetermined desired value.

Electronic circuit, method of controlling electronic circuit, and electronic apparatus

In order to avoid disappearance of output symbols in accompaniment with DC voltage fluctuations occurring at the timing of switching gain in receiving systems for mobile telephones or the like compatible with W-CDMA systems, the present invention provides a variable gain amplifier circuit, a gain control circuit and a mobile communication terminal apparatus, in which a PGA section is comprised of PGAs having different amplification widths continuously arranged in plural stages as in, two coarse adjustment PGAs, a fine adjustment PGA and a coarse adjustment PGA from the input side to the output side; and a gain control circuit has a memory storing a history of gain control with regard to the PGA section and a logic circuit individually controlling gain of each PGA.

Mobile communication terminal apparatus, a variable gain amplifier circuit and a gain control circuit

Disclosed is a delta-sigma modulated fractional-N PLL frequency synthesizer which performs fractional-N by modulating a divider that divides output frequencies from a voltage controlled oscillator. Fractional part data F from a register is forwarded to a second adder. A first adder adds output from a delta-sigma modulator to output therefrom delayed and inverted by a delay inverter to generate an artificially random bit stream averaging zero. The second adder adds fractional part data F to output from the first adder to generate an artificially random data sequence averaging a value of fractional part data. The generated data sequence is forwarded to the delta-sigma modulator. An adder adds integral part data to output from the delta-sigma modulator. Added output is forwarded to the divider.

Growing community of inventors

Kanagawa, Japan

Masahisa Tamura