Socionext Inc.

Masahisa Iida

Masahiro Gion

Toshihiro Nakamura

Taro Fukunaga

In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

Semiconductor integrated circuit device

An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.

A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

Semiconductor integrated circuit device and level shifter circuit

A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.

Semiconductor integrated circuit

In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.

In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M) is connected between an input terminal () receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV). A first PMOS transistor (M) having a low drive capability and a second PMOS transistor (M) having a high drive capability are connected in parallel between a power supply terminal (VDD) supplying 1.8 V and a gate of the NMOS transistor (M). A gate of the first PMOS transistor (M) is connected to the input of the inverter (INV). A gate of the second PMOS transistor (M) is connected to an output of the inverter (INV).

Input circuit

An output transistor () has a source connected to a VDDand a drain connected to an output terminal (). A pre-driver () receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG) to a gate of the output transistor (), the gate signal (SG) transiting between the VDDand a potential (VP) at a power source end (). When a VDDis output from an output node (N) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG) from HIGH to LOW, the drive assist circuit () performs an assist operation in which a potential of the output node (N) is temporarily brought down from VDD

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Yokohama, Japan

Masahisa Iida