Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Masahisa Iida

Masanobu Hirose

Kiyoto Ohta

Yuji Yamasaki

Toshihiro Nakamura

Kenichi Origasa

Hiroyuki Sadakata

Kiyoto Oota

Hakuhei Kawakami

Kiyoto Ota

In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.

Semiconductor memory device

A power generation block configured to generate internal power by a charge pump circuit and a power supply control block configured to control the power generation block are provided. First and second power supply interconnects individually separated from an external power supply interconnect are connected to the power generation block and the power supply control block, respectively. At least any one of the power supply interconnects is provided with a filter section configured to remove noise propagating through the power supply interconnect.

Semicondcutor integrated circuit including power generation block and power supply control block

At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred from the first data latch to an error checking and correcting circuit, and error correction and parity generation are performed in a pipeline process. As a result, the CAS access time and the CAS cycle time are reduced.

In order to latch and store a word line reset level voltage (negative voltage) which is set during reset operation, a word line driver includes PMOS transistors and NMOS transistors. The word line driver further includes a stress-reducing PMOS transistor and an NMOS transistor, and also a word line bias control circuit which controls and activates a supply bias during setting of a word line, start of resetting, and a reset period.

Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.

Semiconductor storage device comprising memory array including normal array and parity array

A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device.

A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read, a sense amplifier for amplifying the read data signal, a selection unit for selecting a data signal having a second number of bits forming a part of the data signal amplified by the sense amplifier, and an error detection/correction unit for performing error detection and correction based on at least a part of the selected data signal having the second number of bits, wherein the selection by the selection unit is performed based on a row address.

A semiconductor storage device according to the present invention comprises a plurality of memory cells each provided with an access transistor in which a source is connected to a bit line and a gate is connected to a word line and a capacitor in which a storage electrode is connected to a drain of the access transistor, the plurality of memory cells being placed in a matrix shape in column and row directions, a sense amplifier circuit connected to the source of the access transistor via the bit line, a bit-line precharge voltage generating circuit for generating a bit-line precharge voltage lower than a sense amplifier supply voltage to be supplied to the sense amplifier circuit and supplying the generated bit-line precharge voltage to the bit line, and a cell plate voltage generating circuit for generating a cell plate voltage set to be lower than the bit-line precharge voltage and supplying the generated cell plate voltage to a plate electrode of the capacitor.

Semiconductor storage device

A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.

In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

There is provided a semiconductor memory device in which a bit line precharge operation is increased in speed, and a layout area is reduced. P-channel transistors () that function as switches are provided in a precharge voltage pumping circuit () included in a bit line precharge voltage generation unit. This enhances a pumping efficiency, and reduces a capacitance area of a pumping capacitor ().

Semiconductor memory device, and semiconductor device with the semiconductor memory device and logic circuit device therein

Semiconductor memory device in which bit lines connected to dynamic memory cells extend left and right of sense amplifier column

A semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a DRAM array. In the array, memory cells are arranged in matrix over the first n-well. Each memory cell includes a p-channel MOS access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, word line driver and first n-well.

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Osaka, Japan

Masahisa Iida